 | 2007 |
|---|
| 11 |       | Tse-Yu Yeh:
Low-Power, High-Performance Architecture of the PWRficient Processor Family.
IEEE Micro 27(2): 69-78 (2007) |
| 1998 |
|---|
| 10 | | Tse-Yu Yeh,
Yale N. Patt:
Alternative Implementations of Two-Level Adaptive Branch Prediction.
25 Years ISCA: Retrospectives and Reprints 1998: 451-461 |
| 9 | | Tse-Yu Yeh,
Yale N. Patt:
Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction.
25 Years ISCA: Retrospectives and Reprints 1998: 87-88 |
| 1994 |
|---|
| 8 | | Po-Yung Chang,
Eric Hao,
Tse-Yu Yeh,
Yale N. Patt:
Branch classification: a new mechanism for improving branch predictor performance.
MICRO 1994: 22-31 |
| 1993 |
|---|
| 7 |  | Tse-Yu Yeh,
Yale N. Patt:
A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History.
ISCA 1993: 257-266 |
| 6 | | Tse-Yu Yeh,
Deborah T. Marr,
Yale N. Patt:
Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache.
International Conference on Supercomputing 1993: 67-76 |
| 5 | | Tse-Yu Yeh,
Yale N. Patt:
Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors.
MICRO 1993: 164-175 |
| 1992 |
|---|
| 4 | | Tse-Yu Yeh,
Yale N. Patt:
Alternative Implementations of Two-Level Adaptive Branch Prediction.
ISCA 1992: 124-134 |
| 3 | | Tse-Yu Yeh,
Yale N. Patt:
A comprehensive instruction fetch mechanism for a processor supporting speculative execution.
MICRO 1992: 129-139 |
| 1991 |
|---|
| 2 | | Michael Butler,
Tse-Yu Yeh,
Yale N. Patt,
Mitch Alsup,
Hunter Scales,
Michael Shebanow:
Single Instruction Stream Parallelism is Greater Than Two.
ISCA 1991: 276-286 |
| 1 | | Tse-Yu Yeh,
Yale N. Patt:
Two-Level Adaptive Training Branch Prediction.
MICRO 1991: 51-61 |
