Kumar Yelamarthi

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2008

3 Kumar Yelamarthi, Chien-In Henry Chen: Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. ISQED 2008: 143-147

2 Kumar Yelamarthi, Chien-In Henry Chen: Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. JCP 3(2): 21-28 (2008)

2007

1 Kumar Yelamarthi, Chien-In Henry Chen: Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. ISQED 2007: 426-431

	2008
3		Kumar Yelamarthi, Chien-In Henry Chen: Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. ISQED 2008: 143-147
2		Kumar Yelamarthi, Chien-In Henry Chen: Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. JCP 3(2): 21-28 (2008)
	2007
1		Kumar Yelamarthi, Chien-In Henry Chen: Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. ISQED 2007: 426-431

Coauthor Index

1 Chien-In Henry Chen [1] [2] [3]