Ender Yilmaz

	2009
3		Ender Yilmaz, Sule Ozev: Adaptive test elimination for analog/RF circuits. DAC 2009: 720-725
2		Ender Yilmaz, Günhan Dündar: Analog Layout Generator for CMOS Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 32-45 (2009)
	2008
1		Ender Yilmaz, Sule Ozev: Dynamic test scheduling for analog circuits for improved test quality. ICCD 2008: 227-233

Coauthor Index

1	Günhan Dündar	[2]
2	Sule Ozev	[1] [3]

Colors in the list of coauthors