Boxue Yin

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2009

3 Zhen Chen, Dong Xiang, Boxue Yin: A power-effective scan architecture using scan flip-flops clustering and post-generation filling. ACM Great Lakes Symposium on VLSI 2009: 517-522

2 Zhen Chen, Boxue Yin, Dong Xiang: Conflict driven scan chain configuration for high transition fault coverage and low test power. ASP-DAC 2009: 666-671

1 Boxue Yin, Dong Xiang, Zhen Chen: New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets. VLSI Design 2009: 221-226

	2009
3		Zhen Chen, Dong Xiang, Boxue Yin: A power-effective scan architecture using scan flip-flops clustering and post-generation filling. ACM Great Lakes Symposium on VLSI 2009: 517-522
2		Zhen Chen, Boxue Yin, Dong Xiang: Conflict driven scan chain configuration for high transition fault coverage and low test power. ASP-DAC 2009: 666-671
1		Boxue Yin, Dong Xiang, Zhen Chen: New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets. VLSI Design 2009: 221-226

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