Tomokazu Yoneda

2008
21	EE	Tomokazu Yoneda, Hideo Fujiwara: Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. DATE 2008: 1366-1369
20	EE	Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara: Scheduling Power-Constrained Tests through the SoC Functional Bus. IEICE Transactions 91-D(3): 736-746 (2008)
19	EE	Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara: Test Scheduling for Multi-Clock Domain SoCs under Power Constraint. IEICE Transactions 91-D(3): 747-755 (2008)
18	EE	Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara: Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. IEICE Transactions 91-D(3): 807-814 (2008)
2007
17	EE	Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara: Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. ASP-DAC 2007: 720-725
16	EE	Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara: A DFT Method for Time Expansion Model at Register Transfer Level. DAC 2007: 682-687
15	EE	Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara: Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. DATE 2007: 231-236
14	EE	Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara: Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. European Test Symposium 2007: 35-42
13	EE	Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara: Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. ISCAS 2007: 2942-2945
12	EE	Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara: Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. VTS 2007: 369-374
11	EE	Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara: TAM Design and Optimization for Transparency-Based SoC Test. VTS 2007: 381-388
2006
10	EE	Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara: A memory grouping method for sharing memory BIST logic. ASP-DAC 2006: 671-676
9	EE	Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara: Power-constrained test scheduling for multi-clock domain SoCs. DATE 2006: 297-302
8	EE	Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara: Power-Constrained SOC Test Schedules through Utilization of Functional Buses. ICCD 2006
7	EE	Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara: A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips. IEICE Transactions 89-D(4): 1490-1497 (2006)
6	EE	Tomokazu Yoneda, Hideo Fujiwara: Design for consecutive transparency method of RTL circuits. Systems and Computers in Japan 37(2): 1-10 (2006)
2005
5	EE	Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara: Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. Asian Test Symposium 2005: 150-155
4	EE	Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara: A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium 2005: 306-311
2003
3	EE	Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara: Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. ITC 2003: 415-422
2	EE	Tomokazu Yoneda, Hideo Fujiwara: Design for Consecutive Transparency of Cores in System-on-a-Chip. VTS 2003: 287-292
2001
1	EE	Tomokazu Yoneda, Hideo Fujiwara: A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. Asian Test Symposium 2001: 193-198

Coauthor Index

1	Hideo Fujiwara	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
2	Ronghua Huang	[13]
3	Fawnizu Azmadi Hussin	[8] [14] [17] [20]
4	Hideyuki Ichihara	[11]
5	Masahiro Imanishi	[15]
6	Tomoo Inoue	[11]
7	Hiroyuki Iwata	[4] [16]
8	Kimihiko Masuda	[9] [19]
9	Masahide Miyazaki	[7] [10]
10	Satoshi Ohtake	[4]
11	Alex Orailoglu	[8] [17] [20]
12	Akiko Shuto	[11]
13	Hisakazu Takakuwa	[5]
14	Tetsuo Uchiyama	[3]
15	Thomas Edison Yu	[12] [18]
16	Dan Zhao	[13]
17	Danella Zhao	[12] [18]