Shingo Yoshizawa

	2008
13		Shingo Yoshizawa, Kazuto Nishi, Yoshikazu Miyanaga: Reconfigurable two-dimensional pipeline FFT processor in OFDM cognitive radio systems. ISCAS 2008: 1248-1251
12		Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga: A complete pipelined MMSE detection architecture in a 4x4 MIMO-OFDM receiver. ISCAS 2008: 2486-2489
11		Chusit Pradabpet, Shingo Yoshizawa, Yoshikazu Miyanaga, Kobchai Dejhan: New PAPR Reduction in OFDM System Using Hybrid of PTS-APPR Methods with Coded Side Information Technique. IEICE Transactions 91-A(10): 2973-2979 (2008)
10		Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga: VLSI Implementation of a Complete Pipeline MMSE Detector for a 4 x 4 MIMO-OFDM Receiver. IEICE Transactions 91-A(7): 1757-1762 (2008)
	2007
9		Takayuki Sugawara, Shingo Yoshizawa, Yoshikazu Miyanaga: Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems. ISCAS 2007: 2287-2290
8		Shingo Yoshizawa, Yoshikazu Miyanaga: Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation. ISCAS 2007: 3175-3178
	2006
7		Shingo Yoshizawa, Yoshikazu Miyanaga: VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System. APCCAS 2006: 93-96
6		Shingo Yoshizawa, Yoshikazu Miyanaga, H. Ochi, Y. Itoh, N. Hataoka, B. Sai, N. Takayama, M. Hirata: 300-Mbps OFDM baseband transceiver for wireless LAN systems. ISCAS 2006
5		Naoya Wada, Noboru Hayasaka, Shingo Yoshizawa, Yoshikazu Miyanaga: Direct control on modulation spectrum for noise-robust speech recognition and spectral subtraction. ISCAS 2006
4		Shingo Yoshizawa, Yoshikazu Miyanaga: Tunable word length architecture for low power wireless OFDM demodulator. ISCAS 2006
3		Shingo Yoshizawa, Yoshikazu Miyanaga: Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator. IEICE Transactions 89-A(10): 2866-2873 (2006)
	2005
2		Yasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga: Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder. ISCAS (1) 2005: 25-28
	2004
1		Shingo Yoshizawa, Naoya Wada, Noboru Hayasaka, Yoshikazu Miyanaga: Scalable architecture for word HMM-based speech recognition. ISCAS (3) 2004: 417-420

Coauthor Index

1	Kobchai Dejhan	[11]
2	Yasuyuki Hatakawa	[2]
3	N. Hataoka	[6]
4	Noboru Hayasaka	[1] [5]
5	M. Hirata	[6]
6	Y. Itoh	[6]
7	Yoshikazu Miyanaga	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
8	Kazuto Nishi	[13]
9	H. Ochi	[6]
10	Chusit Pradabpet	[11]
11	B. Sai	[6]
12	Takayuki Sugawara	[9]
13	N. Takayama	[6]
14	Naoya Wada	[1] [5]
15	Yasushi Yamauchi	[10] [12]