| 2008 | ||
|---|---|---|
| 3 | Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong: FPGA interconnect design using logical effort. FPGA 2008: 257 | |
| 2 | Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong: FPGA interconnect design using logical effort. FPL 2008: 447-450 | |
| 1 | Haile Yu: FPGA interconnect sizing using extended logical effort model. FPL 2008: 695-696 | |
| 1 | Yuk Hei Chan | [2] [3] |
| 2 | Philip Heng Wai Leong | [2] [3] |