Haile Yu

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2008

3 Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong: FPGA interconnect design using logical effort. FPGA 2008: 257

2 Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong: FPGA interconnect design using logical effort. FPL 2008: 447-450

1 Haile Yu: FPGA interconnect sizing using extended logical effort model. FPL 2008: 695-696

	2008
3		Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong: FPGA interconnect design using logical effort. FPGA 2008: 257
2		Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong: FPGA interconnect design using logical effort. FPL 2008: 447-450
1		Haile Yu: FPGA interconnect sizing using extended logical effort model. FPL 2008: 695-696

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