| 2009 | ||
|---|---|---|
| 44 | Ali Jahanian, Morteza Saheb Zamani: Improved performance and yield with chip master planning design methodology. ACM Great Lakes Symposium on VLSI 2009: 185-190 | |
| 43 | Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani: A cycle-based synthesis algorithm for reversible logic. ASP-DAC 2009: 745-750 | |
| 42 | Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani: Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. DATE 2009: 833-838 | |
| 2008 | ||
| 41 | Arash Mehdizadeh, Morteza Saheb Zamani: Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits. AICCSA 2008: 61-68 | |
| 40 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Design space exploration for a coarse grain accelerator. ASP-DAC 2008: 685-690 | |
| 39 | Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi: Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. ASP-DAC 2008: 83-88 | |
| 38 | Ali Jahanian, Morteza Saheb Zamani: Performance and Timing Yield Enhancement using Highway-on-Chip Planning. DSD 2008: 165-172 | |
| 37 | Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi: Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm. DSD 2008: 472-479 | |
| 36 | Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani: Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. DSD 2008: 490-493 | |
| 35 | Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi: An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty. DSD 2008: 558-565 | |
| 34 | Ehsan K. Ardestani, Morteza Saheb Zamani, Mehdi Sedighi: A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. DSD 2008: 803-806 | |
| 33 | Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani: Performance Improvement of Physical Retiming with Shortcut Insertion. ISVLSI 2008: 215-220 | |
| 32 | Arash Mehdizadeh, Morteza Saheb Zamani, Hosein Shafiei: An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme. ISVLSI 2008: 233-238 | |
| 31 | Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi: FPGA-Based Circuit Model Emulation of Quantum Algorithms. ISVLSI 2008: 399-404 | |
| 30 | Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi: Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. ISVLSI 2008: 467-470 | |
| 29 | Yasaman Sanaee, Mehdi Saeedi, Morteza Saheb Zamani: Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions. ISVLSI 2008: 471-474 | |
| 28 | Hamid Fadishei, Mehdi Saeedi, Morteza Saheb Zamani: A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems. Microprocessors and Microsystems - Embedded Hardware Design 32(4): 223-233 (2008) | |
| 27 | Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: An architecture framework for an adaptive extensible processor. The Journal of Supercomputing 45(3): 313-340 (2008) | |
| 2007 | ||
| 26 | Hamid Reza Kheirabadi, Morteza Saheb Zamani: An efficient net ordering algorithm for buffer insertion. ACM Great Lakes Symposium on VLSI 2007: 521-524 | |
| 25 | Ali Jahanian, Morteza Saheb Zamani: Improved timing closure by early buffer planning in floor-placement design flow. ACM Great Lakes Symposium on VLSI 2007: 558-563 | |
| 24 | Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi: Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. DSD 2007: 339-346 | |
| 23 | Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani: A novel synthesis algorithm for reversible circuits. ICCAD 2007: 65-68 | |
| 22 | Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ICESS 2007: 249-260 | |
| 21 | Hamid Reza Kheirabadi, Morteza Saheb Zamani, Mehdi Saeedi: An Efficient Analytical Approach to Path-Based Buffer Insertion. ISVLSI 2007: 219-224 | |
| 20 | Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi: On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. ISVLSI 2007: 428-436 | |
| 19 | Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, Farhad Mehdipour: An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. VLSI-SoC 2007: 151-156 | |
| 18 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. IEICE Transactions 90-D(12): 1956-1966 (2007) | |
| 17 | Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian: Evaluation, prediction and reduction of routing congestion. Microelectronics Journal 38(8-9): 942-958 (2007) | |
| 2006 | ||
| 16 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue: An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference 2006: 219-230 | |
| 15 | Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori: GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. ERSA 2006: 227-230 | |
| 14 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi: Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC 2006: 722-731 | |
| 13 | Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. FPL 2006: 1-4 | |
| 12 | Farhad Mehdipour, Morteza Saheb Zamani, H. R. Ahmadifar, Mehdi Sedighi, Kazuaki Murakami: Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. IPDPS 2006 | |
| 11 | Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian: Prediction and reduction of routing congestion. ISPD 2006: 72-77 | |
| 10 | Ali Jahanian, Morteza Saheb Zamani: Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. ISVLSI 2006: 411-415 | |
| 9 | Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi: An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. Microprocessors and Microsystems 30(1): 52-62 (2006) | |
| 2005 | ||
| 8 | Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabaei: A novel reconfigurable hardware architecture for IP address lookup. ANCS 2005: 81-90 | |
| 7 | Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi: Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. DSD 2005: 372-378 | |
| 6 | Arash Hariri, Reza Rastegar, Keivan Navi, Morteza Saheb Zamani, Mohammad Reza Meybodi: Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution. Evolvable Hardware 2005: 294-297 | |
| 5 | Arash Hariri, Reza Rastegar, Morteza Saheb Zamani, Mohammad Reza Meybodi: Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA. FCCM 2005: 311-314 | |
| 4 | Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour: A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms. FPT 2005: 307-308 | |
| 1995 | ||
| 3 | Morteza Saheb Zamani, Graham R. Hellestrand: A neural network approach to the placement problem. ASP-DAC 1995 | |
| 2 | Morteza Saheb Zamani, Graham R. Hellestrand: A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs. ISCAS 1995: 49-52 | |
| 1 | Morteza Saheb Zamani, Graham R. Hellestrand: A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs. IWANN 1995: 1128-1134 | |