| 2012 | ||
|---|---|---|
| 43 | Chuan Wu, Jialin Cao, Dan Bao, Yun Chen, Xiaoyang Zeng: A 60mW baseband SoC for CMMB receiver. ASP-DAC 2012: 479-480 | |
| 42 | Dan Bao, Xubin Chen, Yuebin Huang, Chuan Wu, Yun Chen, Xiaoyang Zeng: A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS. ASP-DAC 2012: 565-566 | |
| 41 | Huailu Ren, Yibo Fan, Xinhua Chen, Xiaoyang Zeng: A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder. ASP-DAC 2012: 801-806 | |
| 40 | Zhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming-e Jing, Xiaoyang Zeng: An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. ISSCC 2012: 64-66 | |
| 39 | Huibo Zhong, Sha Shen, Yibo Fan, Xiaoyang Zeng: A Low Complexity Macroblock Layer Rate Control Scheme Base on Weighted-Window for H.264 Encoder. MMM 2012: 563-573 | |
| 38 | Wenhua Fan, Chen Chen, Yun Chen, Zhiyi Yu, Xiaoyang Zeng: Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform. IEICE Transactions 95-B(4): 1241-1248 (2012) | |
| 37 | Weiwei Shen, Yibo Fan, Xiaoyang Zeng: A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K × 2 K Applications. IEICE Transactions 95-C(4): 441-446 (2012) | |
| 36 | Yibo Fan, Jialiang Liu, Dexue Zhang, Xiaoyang Zeng, Xinhua Chen: An 8 × 4 Adaptive Hadamard Transform Based FME VLSI Architecture for 4 K × 2 K H.264/AVC Encoder. IEICE Transactions 95-C(4): 447-455 (2012) | |
| 35 | Changsheng Zhou, Yuebin Huang, Shuangqu Huang, Yun Chen, Xiaoyang Zeng: An Area-Efficient Reconfigurable LDPC Decoder with Conflict Resolution. IEICE Transactions 95-C(4): 478-486 (2012) | |
| 34 | Weina Zhou, Lin Dai, Yao Zou, Xiaoyang Zeng, Jun Han: A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm. IEICE Transactions 95-D(2): 383-391 (2012) | |
| 33 | Shuangqu Huang, Xiaoyang Zeng, Yun Chen: A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms. IEICE Transactions 95-D(2): 403-412 (2012) | |
| 2011 | ||
| 32 | Changsheng Zhou, Yunlong Ge, Xubin Chen, Yun Chen, Xiaoyang Zeng: An area-Efficient LDPC decoder for multi-standard with conflict resolution. ASAP 2011: 105-112 | |
| 31 | Dan Bao, Chuan Wu, Yan Ying, Yun Chen, Xiaoyang Zeng: A 4.32 mm2 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications. ASP-DAC 2011: 77-78 | |
| 30 | Zhiyi Yu, Zewen Shi, Xiaoyang Zeng: Fault tolerant computing for stream DSP applications using GALS multi-core processors. ISCAS 2011: 2305-2308 | |
| 29 | Zewen Shi, Yueming Yang, Xiaoyang Zeng, Zhiyi Yu: A reconfigurable and deadlock-free routing algorithm for 2D Mesh Network-on-Chip. ISCAS 2011: 2934-2937 | |
| 28 | Yizhi Wang, Yun Chen, Yunlong Ge, Huxiong Xu, Xiaoyang Zeng: A channel estimation scheme for Chinese DTTB system combating long echo and high doppler shift. ISCAS 2011: 462-465 | |
| 27 | Jialiang Liu, Xinhua Chen, Yibo Fan, Xiaoyang Zeng: A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder. VLSI-SoC 2011: 434-439 | |
| 26 | Jiang Ying, Xinhua Chen, Yibo Fan, Xiaoyang Zeng: MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoder. VLSI-SoC 2011: 72-77 | |
| 25 | Chuan Wu, Dan Bao, Xiaoyang Zeng, Yun Chen: Efficient Iterative Frequency Domain Equalization for Single Carrier System with Insufficient Cyclic Prefix. IEICE Transactions 94-B(7): 2174-2177 (2011) | |
| 24 | Yibo Fan, Xiaoyang Zeng, Satoshi Goto: Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC. IEICE Transactions 94-C(4): 411-418 (2011) | |
| 23 | Zewen Shi, Xiaoyang Zeng, Zhiyi Yu: A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs. IEICE Transactions 94-D(7): 1386-1397 (2011) | |
| 22 | Bo Xiang, Dan Bao, Shuangqu Huang, Xiaoyang Zeng: An 847-955 Mb/s 342-397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 μ m CMOS. J. Solid-State Circuits 46(6): 1416-1432 (2011) | |
| 2010 | ||
| 21 | Bo Xiang, Dan Bao, Shuangqu Huang, Xiaoyang Zeng: A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications. ASAP 2010: 225-232 | |
| 20 | Simeng Li, Huxiong Xu, Wenhua Fan, Yun Chen, Xiaoyang Zeng: A 128/256-point pipeline FFT/IFFT processor for MIMO OFDM system IEEE 802.16e. ISCAS 2010: 1488-1491 | |
| 19 | Zewen Shi, Kaidi You, Yan Ying, Bei Huang, Xiaoyang Zeng, Zhiyi Yu: A scalable and fault-tolerant routing algorithm for NoCs. ISCAS 2010: 165-168 | |
| 18 | Shuangqu Huang, Dan Bao, Bo Xiang, Yun Chen, Xiaoyang Zeng: A flexible LDPC decoder architecture supporting two decoding algorithms. ISCAS 2010: 3929-3932 | |
| 17 | Bo Xiang, Rui Shen, An Pan, Dan Bao, Xiaoyang Zeng: An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes. IEEE Trans. VLSI Syst. 18(10): 1447-1460 (2010) | |
| 16 | Dan Bao, Bo Xiang, Rui Shen, An Pan, Yun Chen, Xiaoyang Zeng: Programmable Architecture for Flexi-Mode QC-LDPC Decoder Supporting Wireless LAN/MAN Applications and Beyond. IEEE Trans. on Circuits and Systems 57-I(1): 125-138 (2010) | |
| 15 | Yan Ying, Dan Bao, Zhiyi Yu, Xiaoyang Zeng, Yun Chen: A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue. IEICE Transactions 93-A(8): 1415-1424 (2010) | |
| 2009 | ||
| 14 | Dan Cao, Jun Han, Xiaoyang Zeng, Shi-ting Lu: A multi-task-oriented security processing architecture with powerful extensibility. ASP-DAC 2009: 133-134 | |
| 2008 | ||
| 13 | Ronghua Lu, Jun Han, Xiaoyang Zeng, Qing Li, Lang Mai, Jia Zhao: A low-cost cryptographic processor for security embedded system. ASP-DAC 2008: 113-114 | |
| 12 | Daxian Yun, Yanjie Peng, Jun Han, Xiaoyang Zeng: Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels. ISCAS 2008: 2490-2493 | |
| 11 | Liang Li, Jun Han, Xiaoyang Zeng, Jia Zhao: A full-custom design of AES SubByte module with signal independent power consumption. ISCAS 2008: 3302-3305 | |
| 10 | Li Qing, Xiaoyang Zeng, Chuan Wu, Yulong Zhang, Yunsong Deng, Jun Han: Optimal frame synchronization for DVB-S2. ISCAS 2008: 956-959 | |
| 2007 | ||
| 9 | Jing Wang, Lang Mai, Yanjie Peng, Jun Han, Xiaoyang Zeng: An Energy-Proportion Synchronization Method for IR-UWB Communications. ISCAS 2007: 2578-2581 | |
| 8 | Yehua Gu, Xiaoyang Zeng, Jun Han, Jia Zhao: A Low-cost and High-performance SoC Design for OMA DRM2 Applications. ISCAS 2007: 3510-3513 | |
| 7 | Jia Zhao, Jun Han, Xiaoyang Zeng, Yunsong Deng: Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation. SiPS 2007: 151-156 | |
| 6 | Yun Chen, Xiaoyang Zeng, An Pan, Jing Wang: A Novel Five-Point Algorithm of Phase Noise Cancellation in DTMB. IEICE Transactions 90-A(11): 2608-2611 (2007) | |
| 2006 | ||
| 5 | Min Wu, Xiaoyang Zeng, Jun Han, Yongyi Wu, Yibo Fan: A high-performance platform-based SoC for information security. ASP-DAC 2006: 122-123 | |
| 4 | Yibo Fan, Xiaoyang Zeng, Yu Yu, Gang Wang, Qianling Zhang: A modified high-radix scalable Montgomery multiplier. ISCAS 2006 | |
| 3 | Yongyi Wu, Xiaoyang Zeng: A new dual-field elliptic curve cryptography processor. ISCAS 2006 | |
| 2 | Yongxin Ma, Xiaoyang Zeng, Min Wu, Chengshou Sun: A new low cost and reconfigurable RSA crypto-processor. ISCAS 2006 | |
| 1 | Jiefeng Yan, Lei Xie, Xiaoyang Zeng, Tingao Tang: Adaptive bandwidth PLL with compact current mode filter. ISCAS 2006 | |
Colors in the list of coauthors
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