| 2008 | ||
|---|---|---|
| 4 | C. N. Zhang, Xiao Wei Liu: Algorithm-Based Fault-Tolerant Cryptography. Wiley Encyclopedia of Computer Science and Engineering 2008 | |
| 2001 | ||
| 3 | C. N. Zhang, W. K. Chou, N. N. Zhang, J. Xie: A DSP Based POD Implementation for High Speed Multimedia Communication. ISCA PDCS 2001: 206-210 | |
| 1994 | ||
| 2 | C. N. Zhang, T. M. Bachtiar, W. K. Chou: An Optimal Fault-Tolerant Design Approach for Array Processors. ICPADS 1994: 348-353 | |
| 1993 | ||
| 1 | C. N. Zhang, Hon F. Li, R. Jayakumar: A Systematic Approach for Designing Concurrent Error-Detecting Systolic Arrays Using Redundancy. Parallel Computing 19(7): 745-764 (1993) | |
| 1 | T. M. Bachtiar | [2] |
| 2 | W. K. Chou | [2] [3] |
| 3 | Rajagopalan Jayakumar (R. Jayakumar) | [1] |
| 4 | Hon F. Li | [1] |
| 5 | Xiao Wei Liu | [4] |
| 6 | J. Xie | [3] |
| 7 | N. N. Zhang | [3] |