 | 2003 |
|---|
| 9 |       | Ramaswamy Govindarajan,
Hongbo Yang,
José Nelson Amaral,
Chihong Zhang,
Guang R. Gao:
Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures.
IEEE Trans. Computers 52(1): 4-20 (2003) |
| 2001 |
|---|
| 8 |  | Ramaswamy Govindarajan,
Hongbo Yang,
Chihong Zhang,
José Nelson Amaral,
Guang R. Gao:
Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs.
IPDPS 2001: 26 |
| 1999 |
|---|
| 7 | | Chihong Zhang,
Ramaswamy Govindarajan,
Sean Ryan,
Guang R. Gao:
Efficient State-Diagram Construction Methods for Software Pipelining.
CC 1999: 153-167 |
| 6 | | Ramaswamy Govindarajan,
Chihong Zhang,
Guang R. Gao:
Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors.
LCPC 1999: 70-84 |
| 1997 |
|---|
| 5 | | Zhizhong Tang,
Chihong Zhang,
Sifei Lvand,
Tao Yu:
A New Architecture For Branch-Intensive Loops.
APDC 1997: 241-247 |
| 4 | | Tao Yu,
Zhizhong Tang,
Chihong Zhang,
Jun Luo:
Control Mechanism for Software Pipelining on Nested Loop.
APDC 1997: 345-350 |
| 3 | | Chihong Zhang,
Zhizhong Tang:
An Improvement on Data Dependence Analysis Supporting Software Pipelining Technique.
APDC 1997: 378-382 |
| 1993 |
|---|
| 2 | | Zhizhong Tang,
Gang Chen,
Chihong Zhang,
Yingwei Zhang,
Bogong Su,
Stanley Habib:
GPMB - software pipelining branch-intensive loops.
MICRO 1993: 21-30 |
| 1 | | Bogong Su,
Jian Wang,
Zhizhong Tang,
Chihong Zhang,
Wei Zhao:
URPR-1: A single-chip VLIW architecture.
Microprocessing and Microprogramming 39(1): 25-41 (1993) |
