 | 2008 |
|---|
| 15 |       | Jiangli Zhu,
Xinmiao Zhang,
Zhongfeng Wang:
Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes.
ICCD 2008: 526-531 |
| 14 | | Jiangli Zhu,
Xinmiao Zhang,
Zhongfeng Wang:
Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes.
ISCAS 2008: 3078-3081 |
| 13 | | Bainan Chen,
Xinmiao Zhang:
FPGA implementation of a factorization processor for soft-decision reed-solomon decoding.
ISCAS 2008: 944-947 |
| 12 | | Xinmiao Zhang,
Jiangli Zhu:
Efficient interpolration architecture for soft-decision Reed-Solomon decoding by applying slow-down.
SiPS 2008: 19-24 |
| 11 | | Bainan Chen,
Xinmiao Zhang,
Zhongfeng Wang:
Error correction for multi-level NAND flash memory using Reed-Solomon codes.
SiPS 2008: 94-99 |
| 2007 |
|---|
| 10 | | Xinmiao Zhang,
Jiangli Zhu:
Low-complexity Interpolation Architecture for Soft-decision Reed-Solomon Decoding.
ISCAS 2007: 1413-1416 |
| 9 | | Jiangli Zhu,
Xinmiao Zhang:
Efficient Interpolation Architecture for Soft-Decision Reed-Solomon Decoding.
SiPS 2007: 663-668 |
| 8 | | Xinmiao Zhang:
Further Exploring the Strength of Prediction in the Factorization of Soft-Decision Reed-Solomon Decoding.
IEEE Trans. VLSI Syst. 15(7): 811-820 (2007) |
| 7 | | Nicolas Sklavos,
Máire McLoone,
Xinmiao Zhang:
MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing.
MONET 12(4): 229-230 (2007) |
| 2006 |
|---|
| 6 | | Xinmiao Zhang:
Partial parallel factorization in soft-decision Reed-Solomon decoding.
ACM Great Lakes Symposium on VLSI 2006: 272-277 |
| 5 | | Xinmiao Zhang:
High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding.
ICCD 2006 |
| 2005 |
|---|
| 4 | | Xinmiao Zhang,
Keshab K. Parhi:
Fast factorization architecture in soft-decision Reed-Solomon decoding.
IEEE Trans. VLSI Syst. 13(4): 413-426 (2005) |
| 3 | | Xinmiao Zhang,
Keshab K. Parhi:
High-Speed Architectures for Parallel Long BCH Encoders.
IEEE Trans. VLSI Syst. 13(7): 872-877 (2005) |
| 2004 |
|---|
| 2 | | Xinmiao Zhang,
Keshab K. Parhi:
High-speed architectures for parallel long BCH encoders.
ACM Great Lakes Symposium on VLSI 2004: 1-6 |
| 1 | | Xinmiao Zhang,
Keshab K. Parhi:
High-speed VLSI architectures for the AES algorithm.
IEEE Trans. VLSI Syst. 12(9): 957-967 (2004) |
