Yexin Zheng

	2009
4		Yexin Zheng, Chao Huang: A novel Toffoli network synthesis algorithm for reversible logic. ASP-DAC 2009: 739-744
3		Yexin Zheng, Chao Huang: Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability. DATE 2009: 1279-1283
	2008
2		Yexin Zheng, Michael S. Hsiao, Chao Huang: SAT-based equivalence checking of threshold logic designs for nanotechnologies. ACM Great Lakes Symposium on VLSI 2008: 225-230
1		Yexin Zheng, Chao Huang: Reconfigurable RTD-based circuit elements of complete logic functionality. ASP-DAC 2008: 71-76

Coauthor Index

1	Michael S. Hsiao	[2]
2	Chao Huang	[1] [2] [3] [4]