| 2008 | ||
|---|---|---|
| 41 | Tracey Y. Zhou, Dian Zhou, Hua Zhang, Xinyue Niu: Foundational-circuit-based spice simulation. ISCAS 2008: 876-879 | |
| 2007 | ||
| 40 | Jun Tao, Xuan Zeng, Wei Cai, Yangfeng Su, Dian Zhou, Charles Chiang: Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations. ASP-DAC 2007: 474-479 | |
| 39 | Hengliang Zhu, Xuan Zeng, Wei Cai, Jintao Xue, Dian Zhou: A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology. DATE 2007: 1514-1519 | |
| 38 | Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, Dian Zhou: Traffic Splitting with Network Calculus for Mesh Sensor Networks. FGCN (2) 2007: 368-373 | |
| 37 | Fan Yang, Xuan Zeng, Yangfeng Su, Dian Zhou: RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect. ISCAS 2007: 2710-2713 | |
| 36 | Ming-e Jing, Yue Hao, Dian Zhou, Xuan Zeng: A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1149-1155 (2007) | |
| 35 | Ming-e Jing, Dian Zhou, PuShan Tang, XiaoFang Zhou, Hua Zhang: Solving SAT problem by heuristic polarity decision-making algorithm. Science in China Series F: Information Sciences 50(6): 915-925 (2007) | |
| 2006 | ||
| 34 | Hengliang Zhu, Xuan Zeng, Wei Cai, Dian Zhou: A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations. APCCAS 2006: 1095-1098 | |
| 33 | Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles Chiang: Time domain model order reduction by wavelet collocation method. DATE 2006: 21-26 | |
| 32 | Jun Tao, Xuan Zeng, Fan Yang, Yangfeng Su, Lihong Feng, Wei Cai, Dian Zhou, Charles Chiang: A one-shot projection method for interconnects with process variations. ISCAS 2006 | |
| 31 | Wei Li, Daniel Blakely, Scott Van Sooy, Keven Dunn, David Kidd, Robert Rogenmoser, Dian Zhou: LVS verification across multiple power domains for a quad-core microprocessor. ACM Trans. Design Autom. Electr. Syst. 11(2): 490-500 (2006) | |
| 2005 | ||
| 30 | Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles Chiang, Dian Zhou: Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. ASP-DAC 2005: 244-249 | |
| 29 | Xuan Zeng, Bank Liu, Jun Tao, Charles Chiang, Dian Zhou: A novel wavelet method for noise analysis of nonlinear circuits. ASP-DAC 2005: 471-476 | |
| 28 | Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng: Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. ISCAS (1) 2005: 113-116 | |
| 27 | Hua Zhang, Dian Zhou, Yi Hu, Ruiming Li, Jianzhong Zhang: Phase noise spectra analysis for LC oscillators. ISCAS (3) 2005: 2263-2266 | |
| 26 | Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng: Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1915-1924 (2005) | |
| 25 | Dian Zhou, Ruiming Li: Design and Verification of High-Speed VLSI Physical Design. J. Comput. Sci. Technol. 20(2): 147-165 (2005) | |
| 2004 | ||
| 24 | Jian Wang, Jun Tao, Xuan Zeng, Charles Chiang, Dian Zhou: Analog circuit behavioral modeling via wavelet collocation method with auto-companding. ASP-DAC 2004: 45-50 | |
| 23 | Ruiming Li, Dian Zhou, Donglei Du: Satisfiability and integer programming as complementary tools. ASP-DAC 2004: 879-882 | |
| 22 | Lihong Feng, Xuan Zeng, Charles Chiang, Dian Zhou, Qiang Fang: Direct Nonlinear Order Reduction with Variational Analysis. DATE 2004: 1316-1321 | |
| 21 | Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles Chiang: Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method. DATE 2004: 1322-1326 | |
| 20 | Yangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles Chiang, Dian Zhou: SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits. ICCAD 2004: 74-79 | |
| 19 | Hua Zhang, Jianzhong Zhang, Dian Zhou, Jin Liu, Liangjun Jiang, Yan Pan: A closed-form phase noise solution for an ideal LC oscillator. ISCAS (4) 2004: 768-771 | |
| 18 | Lihong Feng, Xuan Zeng, Jiarong Tong, Charles Chiang, Dian Zhou: Two-sided projection method in variational equation model order reduction of nonlinear circuits. ISCAS (4) 2004: 816-819 | |
| 17 | Nisar Ahmed, Mohammad H. Tehranipour, Dian Zhou, Mehrdad Nourani: Frequency driven repeater insertion for deep submicron. ISCAS (5) 2004: 181-184 | |
| 16 | Jian Wang, Xuan Zeng, Wei Cai, Charles Chiang, Jiarong Tong, Dian Zhou: Frequency domain wavelet method with GMRES for large-scale linear circuit simulation. ISCAS (5) 2004: 321-324 | |
| 15 | Ronald W. Mehler, Dian Zhou: Automated Architectural Optimization of Digital FIR Filters. VLSI Design 2004: 177-182 | |
| 2003 | ||
| 14 | Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng: Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. ICCAD 2003: 581-587 | |
| 13 | Xuan Zeng, Jun Tao, Yangfeng Su, Wenbing Chen, Dian Zhou: An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation. ISCAS (3) 2003: 168-171 | |
| 12 | Xuan Zeng, Sheng Huang, Yangfeng Su, Dian Zhou: An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method. ISCAS (4) 2003: 664-667 | |
| 2002 | ||
| 11 | Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling: Wavelet method for high-speed clock tree simulation. ISCAS (1) 2002: 177-180 | |
| 2001 | ||
| 10 | Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling: Behavioral Modeling of Analog Circuits by Wavelet Collocation Method. ICCAD 2001: 65-69 | |
| 2000 | ||
| 9 | Haksu Kim, Dian Zhou: Efficient implementation of a planar clock routing with thetreatment of obstacles. IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1220-1225 (2000) | |
| 8 | Xiaoyu Song, Qian-Yu Tang, Dian Zhou, Yuke Wang: Wire space estimation and routability analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 624-628 (2000) | |
| 1999 | ||
| 7 | Haksu Kim, Dian Zhou: An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles. ISCAS (6) 1999: 258-261 | |
| 1995 | ||
| 6 | Zhongli He, Dian Zhou: Optimization of VLSI Allocation. ISCAS 1995: 1065-1068 | |
| 1993 | ||
| 5 | Jason Cong, Kwok-Shing Leung, Dian Zhou: Performance-Driven Interconnect Design Based on Distributed RC Delay Model. DAC 1993: 606-611 | |
| 4 | Dian Zhou, F. Tsui: Neighbour State Transition Method for VLSI Optimization Problems. ICCD 1993: 476-479 | |
| 3 | D. S. Gao, Dian Zhou: Propagation Delay in RLC Interconnection Networks. ISCAS 1993: 2125-2128 | |
| 2 | Dian Zhou, S. Su, F. Tsui, D. S. Gao, Jason Cong: A Two-pole Circuit Model for VLSI High-speed Interconnection. ISCAS 1993: 2129-2132 | |
| 1989 | ||
| 1 | Sanjeev Rao Maddila, Dian Zhou: Routing in general junctions. IEEE Trans. on CAD of Integrated Circuits and Systems 8(11): 1174-1184 (1989) | |