Hai Zhou

	2012
135		Yuankai Chen, Hai Zhou: Buffer minimization in pipelined SDF scheduling on multi-core platforms. ASP-DAC 2012: 127-132
134		Li Li, Yinghai Lu, Hai Zhou: Optimal prescribed-domain clock skew scheduling. ASP-DAC 2012: 523-527
133		Rong Ye, Feng Yuan, Hai Zhou, Qiang Xu: Clock skew scheduling for timing speculation. DATE 2012: 929-934
	2011
132		James Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng: Parallel cross-layer optimization of high-level synthesis and physical design. ASP-DAC 2011: 467-472
131		Li Li, Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng: Low power discrete voltage assignment under clock skew scheduling. ASP-DAC 2011: 515-520
130		Yanling Zhi, Hai Zhou, Xuan Zeng: A practical method for multi-domain clock skew optimization. ASP-DAC 2011: 521-526
129		Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng: Post-routing layer assignment for double patterning. ASP-DAC 2011: 793-798
128		Li Li, Yinghai Lu, Hai Zhou: Optimal multi-domain clock skew scheduling. DAC 2011: 152-157
127		Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng: An efficient algorithm for multi-domain clock skew scheduling. DATE 2011: 1364-1369
126		Yuankai Chen, Hai Zhou, Robert P. Dick: Integrated circuit white space redistribution for temperature optimization. DATE 2011: 613-618
125		Kurt Keutzer, Peng Li, Li Shang, Hai Zhou: A Special Section on Multicore Parallel CAD: Algorithm Design and Programming. ACM Trans. Design Autom. Electr. Syst. 16(3): 21 (2011)
124		Hai Zhou, Kevin Sparks, Nandu Gopalakrishnan, Pantelis Monogioudis, Francis Dominique, Peter Busschbach, Jim Seymour: Deprioritization of heavy users in wireless networks. IEEE Communications Magazine 49(10): 110-117 (2011)
123		Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack: FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. IEEE Trans. VLSI Syst. 19(3): 443-456 (2011)
122		Min Gong, Hai Zhou, Li Li, Jun Tao, Xuan Zeng: Binning Optimization for Transparently-Latched Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 270-283 (2011)
121		Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng: Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 402-415 (2011)
120		Qiang Ma, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou: MSV-Driven Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1152-1162 (2011)
	2010
119		Debasish Das, Jia Wang, Hai Zhou: iRetILP: an efficient incremental algorithm for min-period retiming under general delay model. ASP-DAC 2010: 61-67
118		Jia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang: Hybrid energy storage system integration for vehicles. ISLPED 2010: 369-374
117		Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng: Multicore Parallelization of Min-Cost Flow for CAD Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 29(10): 1546-1557 (2010)
116		Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 466-478 (2010)
	2009
115		Jia Wang, Hai Zhou: Exploring adjacency in floorplanning. ASP-DAC 2009: 367-372
114		Jia Wang, Hai Zhou: Risk aversion min-period retiming under process variations. ASP-DAC 2009: 480-485
113		Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee: Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. ASP-DAC 2009: 636-641
112		Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng: Statistical reliability analysis under process variation and aging effects. DAC 2009: 514-519
111		Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng: Provably good and practically efficient algorithms for CMP dummy fill. DAC 2009: 539-544
110		Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng: Multicore parallel min-cost flow algorithm for CAD applications. DAC 2009: 832-837
109		Yao Zhao, Sagar Vemuri, Jiazhen Chen, Yan Chen, Hai Zhou, Zhi Fu: Exception triggered DoS attacks on wireless networks. DSN 2009: 13-22
108		Hai Zhou: Retiming and resynthesis with sweep are complete for sequential transformation. FMCAD 2009: 192-197
107		Min Gong, Hai Zhou, Jun Tao, Xuan Zeng: Binning optimization based on SSTA for transparently-latched circuits. ICCAD 2009: 328-335
106		Debasish Das, William Scott, Shahin Nazarian, Hai Zhou: An efficient current-based logic cell model for crosstalk delay analysis. ISQED 2009: 627-633
105		Kurt Keutzer, Peng Li, Li Shang, Hai Zhou: ACM Transactions on Design Automation of Electronic Systems (TODAES) special section call for papers: Parallel CAD: Algorithm design and programming. ACM Trans. Design Autom. Electr. Syst. 15(1): (2009)
104		T. Izumi, Hai Zhou, Zuowei Li: Optimal Design of Gear Ratios and Offset for Energy Conservation of an Articulated Manipulator. IEEE T. Automation Science and Engineering 6(3): 551-557 (2009)
103		DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail: A Timing-Dependent Power Estimation Framework Considering Coupling. IEEE Trans. VLSI Syst. 17(6): 843-847 (2009)
102		Jia Wang, Debasish Das, Hai Zhou: Gate Sizing by Lagrangian Relaxation Revisited. IEEE Trans. on CAD of Integrated Circuits and Systems 28(7): 1071-1084 (2009)
	2008
101		Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee: A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications. ASP-DAC 2008: 42-48
100		Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ASP-DAC 2008: 486-491
99		Jia Wang, Hai Zhou: An efficient incremental algorithm for min-area retiming. DAC 2008: 528-533
98		Nikolaos D. Liveris, Hai Zhou, Robert P. Dick, Prithviraj Banerjee: State space abstraction for parameterized self-stabilizing embedded systems. EMSOFT 2008: 11-20
97		Jia Wang, Hai Zhou: Linear constraint graph for floorplan optimization with soft blocks. ICCAD 2008: 9-15
96		Jieyi Long, Hai Zhou, Seda Ogrenci Memik: An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction. ISPD 2008: 126-133
95		Hai Zhou: Circuit Retiming. Encyclopedia of Algorithms 2008
94		Hai Zhou: Circuit Retiming: An Incremental Approach. Encyclopedia of Algorithms 2008
93		Hai Zhou: Rectilinear Spanning Tree. Encyclopedia of Algorithms 2008
92		Hai Zhou: Rectilinear Steiner Tree. Encyclopedia of Algorithms 2008
91		Hai Zhou: A new efficient retiming algorithm derived by formal manipulation. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
90		Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou: Optimizing wirelength and routability by searching alternative packings in floorplanning. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
89		Ruiming Chen, Hai Zhou: Fast Estimation of Timing Yield Bounds for Process Variations. IEEE Trans. VLSI Syst. 16(3): 241-248 (2008)
88		Jieyi Long, Hai Zhou, Seda Ogrenci Memik: EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2169-2182 (2008)
	2007
87		Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007 ACM 2007
86		Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack: NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. ACM Great Lakes Symposium on VLSI 2007: 25-30
85		Jia Wang, Ming-Yang Kao, Hai Zhou: Address generation for nanowire decoders. ACM Great Lakes Symposium on VLSI 2007: 525-528
84		Ruiming Chen, Hai Zhou: Fast Buffer Insertion for Yield Optimization Under Process Variations. ASP-DAC 2007: 19-24
83		Ruiming Chen, Hai Zhou: New Block-Based Statistical Timing Analysis Approaches Without Moment Matching. ASP-DAC 2007: 462-467
82		Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee: Retiming for Synchronous Data Flow Graphs. ASP-DAC 2007: 480-485
81		Chuan Lin, Hai Zhou: Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains. ASP-DAC 2007: 541-546
80		Ruiming Chen, Hai Zhou: Fast Min-Cost Buffer Insertion under Process Variations. DAC 2007: 338-343
79		Chuan Lin, Aiguo Xie, Hai Zhou: Design closure driven delay relaxation based on convex cost network flow. DATE 2007: 63-68
78		Jia Wang, Debasish Das, Hai Zhou: Gate sizing by Lagrangian relaxation revisited. ICCAD 2007: 111-118
77		Ruiming Chen, Hai Zhou: Timing budgeting under arbitrary process variations. ICCAD 2007: 344-349
76		Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou: 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD 2007: 590-597
75		Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou: Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880
74		Ruiming Chen, Hai Zhou: An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2069-2073 (2007)
73		Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou: Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 447-455 (2007)
72		Chuan Lin, Hai Zhou: Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1222-1232 (2007)
71		Jia Wang, Hai Zhou: Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1445-1453 (2007)
70		Debjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1522-1533 (2007)
69		Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou: Unified Incremental Physical-Level and High-Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1576-1588 (2007)
	2006
68		Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006 ACM 2006
67		Jia Wang, Hai Zhou: Optimal jumper insertion for antenna avoidance under ratio upper-bound. DAC 2006: 761-766
66		Chuan Lin, Hai Zhou: An efficient retiming algorithm under setup and hold constraints. DAC 2006: 945-950
65		Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou: Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. DATE 2006: 618-623
64		Chuan Lin, Hai Zhou, Chris C. N. Chu: A revisit to floorplan optimization by Lagrangian relaxation. ICCAD 2006: 164-171
63		Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou: A timing dependent power estimation framework considering coupling. ICCAD 2006: 401-407
62		Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack: FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. ICCD 2006
61		Debjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Random Variables. ISQED 2006: 306-311
60		Jia Wang, Hai Zhou, Ping-Chih Wu: Processing Rate Optimization by Sequential System Floorplanning. ISQED 2006: 340-345
59		Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou: Yield-Aware Cache Architectures. MICRO 2006: 15-25
58		Debjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical Timing Yield Optimization by Gate Sizing. IEEE Trans. VLSI Syst. 14(10): 1140-1146 (2006)
57		Chuan Lin, Jia Wang, Hai Zhou: Clustering for Processing Rate Optimization. IEEE Trans. VLSI Syst. 14(11): 1264-1275 (2006)
56		Debjit Sinha, Hai Zhou: Statistical Timing Analysis With Coupling. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2965-2975 (2006)
55		Ruiming Chen, Hai Zhou: An Efficient Data Structure for Maxplus Merge in Dynamic Programming. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3004-3009 (2006)
54		Debjit Sinha, Hai Zhou: Gate-size optimization under timing constraints for coupling-noise reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1064-1074 (2006)
53		Chuan Lin, Hai Zhou: Optimal wire retiming without binary search. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1577-1588 (2006)
52		Ruiming Chen, Hai Zhou: Statistical timing verification for transparently latched circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1847-1855 (2006)
	2005
51		Jia Wang, Hai Zhou: Interconnect estimation without packing via ACG floorplans. ASP-DAC 2005: 1152-1155
50		Debjit Sinha, Hai Zhou: Yield driven gate sizing for coupling-noise reduction under uncertainty. ASP-DAC 2005: 192-197
49		Hai Zhou: Deriving a new efficient algorithm for min-period retiming. ASP-DAC 2005: 990-993
48		Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee: An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. Asian Test Symposium 2005: 28-33
47		Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee: Leakage power optimization with dual-Vth library in high-level synthesis. DAC 2005: 202-207
46		Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou: Incremental exploration of the combined physical and behavioral design space. DAC 2005: 208-213
45		Debjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical gate sizing for timing yield optimization. ICCAD 2005: 1037-1041
44		Chuan Lin, Jia Wang, Hai Zhou: Clustering for processing rate optimization. ICCAD 2005: 189-195
43		Ruiming Chen, Hai Zhou: Efficient algorithms for buffer insertion in general circuits based on network flow. ICCAD 2005: 322-326
42		Chuan Lin, Hai Zhou: Trade-off between latch and flop for min-period sequential circuit designs with crosstalk. ICCAD 2005: 329-334
41		Debjit Sinha, Hai Zhou: A unified framework for statistical timing analysis with coupling and multiple input switching. ICCAD 2005: 837-843
40		Min Pan, Chris C. N. Chu, Hai Zhou: Timing yield estimation using statistical static timing analysis. ISCAS (3) 2005: 2461-2464
39		Chuan Lin, Hai Zhou: Wire retiming as fixpoint computation. IEEE Trans. VLSI Syst. 13(12): 1340-1348 (2005)
38		Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang: Spanning graph-based nonrectilinear steiner tree algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1066-1075 (2005)
	2004
37		Jia Wang, Hai Zhou: Minimal period retiming under process variations. ACM Great Lakes Symposium on VLSI 2004: 131-135
36		Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang: Efficient octilinear Steiner tree construction based on spanning graphs. ASP-DAC 2004: 687-690
35		Chuan Lin, Hai Zhou: Wire Retiming for System-on-Chip by Fixpoint Computation. DATE 2004: 1092-1097
34		Debjit Sinha, Hai Zhou: Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. ICCAD 2004: 14-19
33		Ruiming Chen, Hai Zhou: Timing macro-modeling of IP blocks with crosstalk. ICCAD 2004: 155-159
32		Chuan Lin, Hai Zhou: Optimal wire retiming without binary search. ICCAD 2004: 452-458
31		Ruiming Chen, Hai Zhou: Clock schedule verification under process variations. ICCAD 2004: 619-625
30		Ruiming Chen, Hai Zhou: A Flexible Data Structure for Efficient Buffer Insertion. ICCD 2004: 216-221
29		Hai Zhou, Jia Wang: ACG-Adjacent Constraint Graph for General Floorplans. ICCD 2004: 572-575
28		Debjit Sinha, Hai Zhou, Chris C. N. Chu: Optimal gate sizing for coupling-noise reduction. ISPD 2004: 176-181
27		Hai Zhou: Efficient Steiner tree construction based on spanning graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 704-710 (2004)
26		Hai Zhou, Chuan Lin: Retiming for wire pipelining in system-on-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1338-1345 (2004)
	2003
25		Hai Zhou: Timing Verification with Crosstalk for Transparently Latched Circuits. DATE 2003: 10056-10061
24		Chuan Lin, Hai Zhou: Retiming for Wire Pipelining in System-On-Chip. ICCAD 2003: 215-220
23		Hai Zhou: Efficient Steiner tree construction based on spanning graphs. ISPD 2003: 152-157
22		Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal: BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. Formal Methods in System Design 22(3): 205-224 (2003)
21		Hai Zhou: Timing analysis with crosstalk is a fixpoint on a complete lattice. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1261-1269 (2003)
	2002
20		Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou: Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD 2002: 59-66
19		Hai Zhou: Clock schedule verification with crosstalk. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 78-83
18		Hai Zhou, Narendra V. Shenoy, William Nicholls: Efficient minimum spanning tree construction without Delaunay triangulation. Inf. Process. Lett. 81(5): 271-276 (2002)
	2001
17		Hai Zhou, Narendra V. Shenoy, William Nicholls: Efficient minimum spanning tree construction without Delaunay triangulation. ASP-DAC 2001: 192-197
16		Hai Zhou, Narendra V. Shenoy, William Nicholls: Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. DAC 2001: 714-719
15		Hai Zhou, Adnan Aziz: Buffer minimization in pass transistor logic. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 693-697 (2001)
	2000
14		Hai Zhou, D. F. Wong: Optimal low power X OR gate decomposition. DAC 2000: 104-107
13		Hai Zhou, Adnan Aziz: Buffer minimization in pass transistor logic. ISPD 2000: 105-110
12		Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous routing and buffer insertion with restrictions onbuffer locations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 819-824 (2000)
	1999
11		Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC 1999: 96-99
10		Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357
9		I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou: An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD 1999: 210-215
8		Hai Zhou, Martin D. F. Wong: Global routing with crosstalk constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1683-1688 (1999)
	1998
7		Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal: BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. CAV 1998: 244-255
6		Hai Zhou, D. F. Wong: Global Routing with Crosstalk Constraints. DAC 1998: 374-377
5		Hai Zhou, D. F. Wong: Optimal river routing with crosstalk constraints. ACM Trans. Design Autom. Electr. Syst. 3(3): 496-514 (1998)
	1997
4		Hai Zhou, D. F. Wong: An exact gate decomposition algorithm for low-power technology mapping. ICCAD 1997: 575-580
3		Hai Zhou, D. F. Wong: Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. ICCD 1997: 628-633
	1996
2		Hai Zhou, D. F. Wong: An optimal algorithm for river routing with crosstalk constraints. ICCAD 1996: 310-315
1		Chung-Ping Chen, Hai Zhou, D. F. Wong: Optimal non-uniform wire-sizing under the Elmore delay model. ICCAD 1996: 38-43

Coauthor Index

1	Jonathan Adams	[59]
2	Adnan Aziz	[7] [9] [11] [12] [13] [15] [22]
3	Prithviraj Banerjee (Prith Banerjee)	[47] [48] [65] [73] [82] [98] [101] [113]
4	Shabbir H. Batterywala	[20] [75]
5	Peter Busschbach	[124]
6	Charlie Chung-Ping Chen (Chung-Ping Chen)	[1]
7	Hung-Ming Chen	[10]
8	Jiazhen Chen	[109]
9	Ruiming Chen	[30] [31] [33] [43] [52] [55] [74] [77] [80] [83] [84] [89]
10	Yan Chen	[109]
11	Yuankai Chen	[126] [135]
12	Chris C. N. Chu (Chris Chu, Chris Chong-Nuen Chu)	[28] [40] [64]
13	Debasish Das	[62] [78] [86] [100] [102] [106] [116] [119] [123]
14	Robert P. Dick	[46] [69] [76] [98] [126]
15	Francis Dominique	[124]
16	Chunyang Feng	[111] [121]
17	Zhi Fu	[109]
18	Anuj Goel	[7] [22]
19	Min Gong	[107] [122]
20	Nandu Gopalakrishnan	[124]
21	Zhenyu (Peter) Gu	[46] [69]
22	Xianlong Hong	[36] [38] [76]
23	Yehea I. Ismail	[62] [63] [68] [86] [103] [123]
24	T. Izumi	[104]
25	Abhijit Jas	[100] [116]
26	Tong Jing	[36] [38]
27	Ming-Yang Kao	[85]
28	Chandramouli V. Kashyap	[100] [116]
29	Kurt Keutzer	[105] [125]
30	DiaaEldin Khalil	[63] [103]
31	Kip Killpack	[62] [86] [100] [116] [123]
32	Kun Li	[118]
33	Li Li	[122] [128] [131] [134]
34	Peng Li	[105] [125]
35	Zhuoyuan Li	[76]
36	Zuowei Li	[104]
37	Chuan Lin	[24] [26] [32] [35] [39] [42] [44] [53] [57] [64] [66] [72] [79] [81] [82]
38	I-Min Liu	[9] [11] [12]
39	Nikolaos D. Liveris	[48] [82] [98] [101] [113]
40	Jieyi Long	[88] [96]
41	Yinghai Lu	[110] [112] [117] [128] [129] [131] [132] [134]
42	Wai-Shing Luk	[127]
43	Jianfeng Luo	[75]
44	Qin Lv	[118]
45	Yuchun Ma	[76]
46	Qiang Ma	[120]
47	Enrico Macii	[87]
48	Arindam Mallik	[65] [73]
49	Yehia Massoud	[87]
50	Gokhan Memik	[59]
51	Seda Ogrenci Memik (Seda Ogrenci)	[88] [96]
52	Pantelis Monogioudis	[124]
53	Shahin Nazarian	[106]
54	William Nicholls	[16] [17] [18] [20]
55	Serkan Ozdemir	[59]
56	Min Pan	[40]
57	Zaichen Qian	[120]
58	Gang Qu	[68]
59	Subramanian Rajagopalan	[75]
60	Khurram Sajid	[7] [22]
61	William Scott	[106]
62	Jim Seymour	[124]
63	Chiu-Wing Sham	[90]
64	Li Shang	[76] [105] [110] [112] [117] [118] [125] [132]
65	Ahmed Shebaita	[62] [86] [123]
66	Narendra V. Shenoy	[16] [17] [18] [20] [45] [58] [61] [70] [75]
67	Naveed A. Sherwani	[10]
68	Vigyan Singhal	[7] [22]
69	Debjit Sinha	[28] [34] [41] [45] [50] [54] [56] [58] [59] [61] [63] [65] [70] [73] [75] [103]
70	Kevin Sparks	[124]
71	Jian Sun	[129] [131]
72	Xiaoyong Tang	[47]
73	Jun Tao	[107] [111] [121] [122]
74	Sagar Vemuri	[109]
75	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[68]
76	J. Wang	[82]
77	Jia Wang	[29] [37] [44] [46] [51] [57] [60] [67] [69] [71] [78] [85] [97] [99] [102] [114] [115] [118] [119]
78	James Williamson	[132]
79	Martin D. F. Wong (D. F. Wong)	[1] [2] [3] [4] [5] [6] [8] [9] [10] [11] [12] [14]
80	Ping-Chih Wu	[60]
81	Aiguo Xie	[79]
82	Qiang Xu	[133]
83	Changhao Yan	[111] [121] [127]
84	Zhiyuan Yan	[87]
85	Fan Yang	[112]
86	Hannah Honghua Yang (Honghua Yang)	[10]
87	Yang Yang	[36] [38]
88	Rong Ye	[133]
89	Evangeline F. Y. Young (F. Y. Young, Fung Yu Young)	[10] [90] [120]
90	Feng Yuan	[133]
91	Xuan Zeng	[107] [110] [111] [112] [117] [121] [122] [127] [129] [130] [131] [132]
92	Yao Zhao	[109]
93	Yanling Zhi	[127] [130]
94	Pingqiang Zhou	[76]
95	Qiang Zhou	[76]
96	Hengliang Zhu	[112] [127]
97	Qi Zhu	[36] [38]

Colors in the list of coauthors

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