Zeljko Zilic

	2009
56		Mohammad Hossein Neishaburi, Zeljko Zilic: Reliability aware NoC router architecture using input channel buffer sharing. ACM Great Lakes Symposium on VLSI 2009: 511-516
55		Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic: MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI 2009: 75-80
54		Atanu Chattopadhyay, Zeljko Zilic: Serial reconfigurable mismatch-tolerant clock distribution. DAC 2009: 611-612
53		Yongquan Fan, Zeljko Zilic: Accelerating jitter tolerance qualification for high speed serial interfaces. ISQED 2009: 360-365
	2008
52		Atanu Chattopadhyay, Zeljko Zilic: Built-in Clock Skew System for On-line Debug and Repair. DATE 2008: 248-251
51		Marc Boule, Zeljko Zilic: Automata-based assertion-checker synthesis of PSL properties. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
50		Stephan Bourduas, Jean-Samuel Chenard, Zeljko Zilic: A Quality-Driven Design Approach for NoCs. IEEE Design & Test of Computers 25(5): 416-428 (2008)
	2007
49		Stephan Bourduas, Zeljko Zilic: Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing. ASAP 2007: 302-307
48		Marc Boule, Zeljko Zilic: Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. ASP-DAC 2007: 324-329
47		Henry H. Y. Chan, Zeljko Zilic: Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. DAC 2007: 430-435
46		Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur: Reversible circuit technology mapping from non-reversible specifications. DATE 2007: 558-563
45		Henry H. Y. Chan, Zeljko Zilic: A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits. ISCAS 2007: 2934-2937
44		Atanu Chattopadhyay, Zeljko Zilic: Reconfigurable Clock Distribution Circuitry. ISCAS 2007: 877-880
43		Marc Boule, Jean-Samuel Chenard, Zeljko Zilic: Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. ISQED 2007: 613-620
42		Stephan Bourduas, Zeljko Zilic: A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing. NOCS 2007: 195-204
41		Zeljko Zilic, Katarzyna Radecka: Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. IEEE Trans. Computers 56(2): 202-207 (2007)
	2006
40		Marc Boule, Jean-Samuel Chenard, Zeljko Zilic: Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. ICCD 2006
39		Rong Zhang, Zeljko Zilic, Katarzyna Radecka: Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. VTS 2006: 186-191
38		Knockaert Radecka, Zeljko Zilic: Arithmetic transforms for compositions of sequential and imprecise datapaths. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1382-1391 (2006)
	2005
37		Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic: Design methodology for wireless nodes with printed antennas. DAC 2005: 291-296
36		Marc Boule, Zeljko Zilic: Incorporating Ef.cient Assertion Checkers into Hardware Emulation. ICCD 2005: 221-228
35		Henry H. Y. Chan, Zeljko Zilic: Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization. ISQED 2005: 390-395
34		Jean-Samuel Chenard, Ahmed Usman Khalid, M. Prokic, Rong Zhang, K.-L. Lim, Atanu Chattopadhyay, Zeljko Zilic: Expandable and Robust Laboratory for Microprocessor Systems. MSE 2005: 65-66
33		Atanu Chattopadhyay, Zeljko Zilic: GALDS: a complete framework for designing multiclock ASICs and SoCs. IEEE Trans. VLSI Syst. 13(6): 641-654 (2005)
	2004
32		Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka: FPGA Emulation of Quantum Circuits. ICCD 2004: 310-315
31		Yongquan Fan, Zeljko Zilic: A novel scheme of implementing high speed AWGN communication channel emulators in FPGAs. ISCAS (2) 2004: 877-880
30		Henry H. Y. Chan, Zeljko Zilic: Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach. ISQED 2004: 309-314
29		Yongquan Fan, Zeljko Zilic, Man Wah Chiang: A Versatile High Speed Bit Error Rate Testing Scheme. ISQED 2004: 395-400
28		Stuart McCracken, Zeljko Zilic: Design for Testability of FPGA Blocks. ISQED 2004: 86-91
27		Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka: Architectures of Increased Availability Wireless Sensor Network Nodes. ITC 2004: 1232-1241
26		Katarzyna Radecka, Zeljko Zilic: Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. IEEE Trans. Computers 53(5): 628-640 (2004)
	2003
25		Atanu Chattopadhyay, Zeljko Zilic: A globally asynchronous locally dynamic system for ASICs and SoCs. ACM Great Lakes Symposium on VLSI 2003: 176-181
24		Yongquan Fan, Zeljko Zilic: Testing for bit error rate in FPGA communication interfaces. FPGA 2003: 243
23		Man Wah Chiang, Zeljko Zilic: Layered Approach to Designing System Test Interfaces. VTS 2003: 331-338
	2002
22		Stuart McCracken, Zeljko Zilic: FPGA test time reduction through a novel interconnect testing scheme. FPGA 2002: 136-144
21		Katarzyna Radecka, Zeljko Zilic: Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. ICCAD 2002: 128-131
20		Zeljko Zilic, Katarzyna Radecka: The Role of Super-Fast Transforms in Speeding Up Quantum Computations. ISMVL 2002: 129-135
19		Boris Polianskikh, Zeljko Zilic: Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection. ISMVL 2002: 89-95
18		Katarzyna Radecka, Zeljko Zilic: Identifying Redundant Wire Replacements for Synthesis and Verification. VLSI Design 2002: 517-523
17		Zeljko Zilic, Zvonko G. Vranesic: A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. IEEE Trans. Computers 51(9): 1100-1105 (2002)
	2001
16		Katarzyna Radecka, Zeljko Zilic: Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. ICCD 2001: 348-353
15		Ian Brynjolfson, Zeljko Zilic: A new PLL design for clock management applications. ISCAS (4) 2001: 814-817
14		Zeljko Zilic, Katarzyna Radecka: : Identifying redundant gate replacements in verification by error modeling. ITC 2001: 803-812
	2000
13		Ian Brynjolfson, Zeljko Zilic: FPGA clock management for low power applications (poster abstract). FPGA 2000: 219
12		R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: The NUMAchine Multiprocessor. ICPP 2000: 487-496
11		Katarzyna Radecka, Zeljko Zilic: Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. VTS 2000: 271-280
	1999
10		Zeljko Zilic, Katarzyna Radecka: On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. ISSAC 1999: 67-74
9		Zeljko Zilic: Alternatives in Teaching System-Building Skills. MSE 1999: 57-58
	1998
8		A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69
7		Zeljko Zilic, Zvonko G. Vranesic: Using Decision Diagrams to Design ULMs for FPGAs. IEEE Trans. Computers 47(9): 970-982 (1998)
	1996
6		Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic: Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. DAC 1996: 427-432
5		Zeljko Zilic, Zvonko G. Vranesic: Using BDDs to Design ULMs for FPGAs. FPGA 1996: 24-30
4		Zeljko Zilic, Zvonko G. Vranesic: New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. ISMVL 1996: 16-23
	1995
3		Zeljko Zilic, Zvonko G. Vranesic: Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. ISMVL 1995: 36-43
2		Zeljko Zilic, Zvonko G. Vranesic: A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. IEEE Trans. Computers 44(8): 1012-1020 (1995)
	1993
1		Zeljko Zilic, Zvonko G. Vranesic: Current-Mode CMOS Galois Field Circuits. ISMVL 1993: 245-250

Coauthor Index

1	Tarek S. Abdelrahman	[12]
2	Dominique Borrione	[55]
3	Marc Boule	[36] [40] [43] [48] [51] [55]
4	Stephan Bourduas	[42] [49] [50]
5	Stephen Dean Brown	[6] [8] [12]
6	Ian Brynjolfson	[13] [15]
7	S. Caranci	[6] [8] [12]
8	Henry H. Y. Chan	[30] [35] [45] [47]
9	Atanu Chattopadhyay	[25] [33] [34] [44] [52] [54]
10	Jean-Samuel Chenard	[27] [34] [37] [40] [43] [50]
11	Man Wah Chiang	[23] [27] [29]
12	Chun Yiu Chu	[37]
13	D. DeVries	[12]
14	Yongquan Fan	[24] [29] [31] [53]
15	Benjamin Gamsa	[12]
16	A. Grbic	[6] [8] [12]
17	R. Grindley	[6] [8] [12]
18	M. Gusat	[6] [8] [12]
19	R. Ho	[12]
20	Ali Kazamiphur	[46]
21	Ahmed Usman Khalid	[32] [34]
22	Orran Krieger	[12]
23	Guy G. Lemieux	[8] [12]
24	K.-L. Lim	[34]
25	K. Loveless	[6] [8] [12]
26	Naraig Manjikian	[6] [8] [12]
27	Stuart McCracken	[22] [28]
28	P. McHardy	[12]
29	Katell Morin-Allory	[55]
30	Mohammad Hossein Neishaburi	[56]
31	Yann Oddos	[55]
32	Boris Polianskikh	[19]
33	Milica Popovic	[37]
34	M. Prokic	[34]
35	Katarzyna Radecka	[10] [11] [14] [16] [18] [20] [21] [26] [27] [32] [39] [41] [46]
36	Knockaert Radecka	[38]
37	Sinisa Srbljic	[6] [8] [12]
38	Michael Stumm	[8] [12]
39	Zvonko G. Vranesic	[1] [2] [3] [4] [5] [6] [7] [8] [12] [17]
40	Rong Zhang	[34] [39]

Colors in the list of coauthors