Volume 23,
Number 1,
2004
Volume 23,
Number 2,
2004
- Juan Manuel Dodero, Miguel-Ángel Sicilia, Camino Fernández:
On the Use of the Choquet Integral for the Collaborative Creation of Learning Objects.
- Li Chunlin, Li Layuan:
Market Mechanism for Dynamic Resource Management In Computational Grid.
- Martin Knor, Ludovít Niepel:
Independence Number in Path Graphs.
- Patrick Brézillon:
Context and Virtual Communities In a Firm.
- Evelio J. González, Alberto F. Hamilton, Lorenzo Moreno, Roberto L. Marichal, Jonay Toledo:
Ontologies in a Multi-Agent System for Automated Scheduling.
- Jing Zheng, Xieng Lu, Kan Yang, Yijie Wang:
A Dynamic Adaptive Replica Allocation Algorithm in Mobile Ad Hoc Networks.
Volume 23,
Number 3,
2004
Volume 23,
Number 4,
2004
- Ricardo Aler, David Camacho, Alfredo Moscardini:
The Effects of Transfer of Global Improvements in Genetic Programming.
- Tae-Kyung Kim, Hyung-Jin Lim, Tai-Myung Chung:
Service Negotiation Model for Response Time in Distributed Networks.
- Hyunseung Choo, JungHyun Han:
Forwarding Based Data Parallel Handoff for Real-Time QoS in Mobile IPv6 Networks.
- Jahwan Koo, Seong-Jin Ahn, Jin-Wook Chung:
A Comparative Study of Queue, Delay, and Loss Characteristics of AQM Schemes in QoS-enabled Networks.
- Mohamed Amin, Rokaia Abd El Mouaty:
Stratified Grammar Systems with Simple and Dynamically Organized Strata.
- Jason J. Jung:
An Application of Collaborative Web Browsing Based on Ontology Learning from User Activities on the Web.
- Gunther Stuer, Jan Broeckhove, Vaidy S. Sunderam:
Publishing H2O Pluglets in UDDI Registries.
Volume 23,
Number 5,
2004
- Heikki Kariniemi, Jari Nurmi:
Performance Evaluation and Implementation of Two Adaptive Routing Algorithms for XGFT Networks.
- Solaiman Rahim, Bruno Rouzeyre, Lionel Torres:
A Flip-Flop Matching Engine to Verify Sequential Optimizations.
- Lukás Sekanina, Stepan Friedl:
An Evolvable Combinational Unit for FPGAs.
- Nele Mentens, Siddika Berna Örs, Bart Preneel, Joos Vandewalle:
An FPGA Implementation of a Montgomery Multiplier Over GF(2^m).
- Milos Drutarovský, Martin Simka, Viktor Fischer, Frederic Celle:
A Simple PLL-Based True Random Number Generator for Embedded Digital Systems.
- Thomas Kottke, Andreas Steininger:
A Generic Dual Core Architecture with Error Containment.
- A. Parreira, João Paulo Teixeira, Marcelino B. Santos:
Built-In Self-Test Quality Assessment Using Hardware Fault Emulation In FPGAs.
- Abhijit Ray, Wu Jigang, Thambipillai Srikanthan:
Knapsack Model and Algorithm for Hardware/Software Partitioning Problem.
Copyright © Sat Nov 14 05:44:58 2009
by Michael Ley (ley@uni-trier.de)