IEEE Design & Test of Computers, Volume 13

Volume 13, Number 1, 1996

• John W. Sheppard: SCC20 attracts IEC participation. 2-

• Masaharu Imai, Eugenio Villar: ASPDAC 1995: HDL synthesizability and interoperability. 3-4

• Yervant Zorian, Jan Hlavicka: Guest Editors' Introduction: East Meets West. 5-7
• Tibor Bartos, Norbert Fristacky:
  Verifying Timing Consistency in Formal Specifications. 8-15
  
• Stanislaw J. Piestrak:
  Self-Checking Design in Eastern Europe. 16-25
  
• Anatoly Prihozhy:
  Net Scheduling in High-Level Synthesis. 26-35
  
• Sergiu Radu, Viorel Onofrei, Mihai Albulet:
  Interconnection Problems in Modern Computers. 36-46
  
• Raimund Ubar:
  Test Synthesis with Alternative Graphs. 48-57
  

• Mick Tegethoff, Tom Chen:
  Sensitivity Analysis of Critical Parameters in Board Test. 58-63
  
• Joseph A. Mielke:
  Frequency Domain Testing of ADCs. 64-69
  
• Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth:
  Fast Power Estimation of Large Circuits. 70-78
  
• Kenneth M. Thompson:
  Intel and the Myths of Test. 79-81
  

• IEEE Design & Test of Computers. 82-83

• Design Automation Technical Committee Newsletter. 84-85

• Test Technology Tc Newsletter. 86-87

• Scott Davidson: Base 1 logic: A method for environmentally friendly PC design. 88-

Volume 13, Number 2, 1996

• Kenneth D. Wagner, Yervant Zorian: EIC Message. 2-

• Vishwani D. Agrawal: 1995 Asian Test Symposium carves a niche. 3-

• Hugo De Man: Submicron design tools: problems and suppliers. 4, 91

• Ajit M. Prabhu, Richard L. Campbell: Management Perspectives in EDA. 5-7, 90-91

• Bozena Kaminska, Bernard Courtois: Guest Editors' Introduction: Mixed Analog and Digital Systems. 8-9
• Thomas Olbrich, Andrew M. D. Richardson:
  Design and Self-Test for Switched-Current Building Blocks. 10-17
  
• Ashok Balivada, Jin Chen, Jacob A. Abraham:
  Analog Testing with Time Response Parameters. 18-25
  
• Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi:
  DC Built-In Self-Test for Linear Analog Circuits. 26-33
  
• Yukiya Miura:
  Real-Time Current Testing for A/D Converters. 34-41
  

• Stephen Dean Brown, Jonathan Rose:
  FPGA and CPLD Architectures: A Tutorial. 42-57
  
• Raul San Martin, John P. Knight:
  Optimizing Power in ASIC Behavioral Synthesis. 58-70
  
• Paul E. Landman, Renu Mehra, Jan M. Rabaey:
  An Integrated CAD Environment for Low-Power Design. 72-82
  
• A D&T Roundtable Deep-Submicron Design. 83-89

• Design Automation Technical Committee Newsletter. 93-

• Test Technology Tc Newsletter. 94-95

• Scott Davidson:
  A test puzzle for a TGIF morning. 96-
  

Volume 13, Number 3, 1996

• News. 4, 109

• Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov: Panel Summaries. 6, 110-112

• Gil Philips, Yervant Zorian, Charles W. Rosenthal, Bozena Kaminska: Conference Reports. 8, 113-144

• Vijay K. Madisetti, Mark A. Richards: Guest Editors' Introduction: Advances in Rapid Prototyping of Digital Systems. 9-11
• Vijay K. Madisetti:
  Rapid Digital System Prototyping: Current Practice, Future Challenges. 12-22
  
• James H. M. Malley:
  RASSP: Changing the Paradigm of Electronic-System Design. 23-31
  
• Richard M. Sedmak, John S. Evans:
  Spanning the Product Life Cycle: RASSP DFT. 32-42
  
• Carolyn Kuttner:
  Hardware-Software Codesign Using Processor Synthesis. 43-53
  
• Lan-Rong Dung, Vijay K. Madisetti:
  Conceptual Prototyping of Scalable Embedded DSP Systems. 54-65
  
• Sandi Habinc, Peter Sinander:
  Using VHDL for Board Level Simulation. 66-78
  

• Harald P. E. Vranken, Marc F. Witteman, Ronald C. van Wuijtswinkel:
  Design for Testability in Hardware-Software Systems. 79-87
  
• Ramesh Karri, Karin Högstedt, Alex Orailoglu:
  Computer-Aided Design of Fault-Tolerant VLSI Systems. 88-96
  
• Adam Cron:
  A D&T Special Report: P1149.4 Mixed-Signal Test Bus. 98-101
  
• A D&T Roundtable: Deep-Submicron Test in cooperation with the Test Technology Technical Committee. 102-108

• Design Automation Technical Committee Newsletter. 116-117

• Test Technology Tc Newsletter. 118-119

• Scott Davidson: How to achieve 95% fault coverage without really trying. 120-

Volume 13, Number 4, 1996

• News. 3-4, 88

• Bernard Courtois: Second Therminic Workshop. 5-

• Harold S. Stone:
  Designing in the multimedia era. 6-7
  
• Wojciech Maly:
  The future of IC design, testing, and manufacturing. 8, 89-91
  

• Stephen Dean Brown:
  FPGA Architectural Research: A Survey. 9-15
  
• Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic:
  Minimizing FPGA Interconnect Delays. 16-23
  
• Todd A. DeLong, Barry W. Johnson, Joseph A. Profeta III:
  A Fault Injection Technique for VHDL Behavioral-Level Models. 24-33
  
• Jacob M. Velixon:
  Transmission Coefficient Correction for DACs. 34-39
  
• Karim Arabi, Bozena Kaminska, Janusz Rzeszut:
  BIST for D/A and A/D Converters. 40-49
  
• Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
  Circular Self-Test Path for FSMs. 50-60
  
• Jerry M. Soden, Charles F. Hawkins:
  IDDQ Testing: Issues Present and Future. 61-65
  
• Koji Nakamae, Homare Sakamoto, Hiromu Fujioka:
  How ATE Planning Affects LSI Manufacturing Cost. 66-73
  
• A D&T Roundtable: Telecommunications System Design. 74-81
• IEEE Design & Test of Computers 1996 Annual Index, Volume 13. 82-85

• Author Guidelines IEEE Design & Test of Computers. 86-87

• Design Automation Technical Committee Newsletter. 93-

• Test Technology Tc Newsletter. 94-95

• Robert C. Aitken:
  When tools cry wolf: Testability pitfalls of synthesized designs. 96-