IEEE Design & Test of Computers, Volume 14

Volume 14, Number 1, January-March 1997

• Keeping in touch: Reader survey results; planned e-mail survey. 4-5

• J. Wilson:
  CFI leads development of design data standard. 6, 91
  

• News. 7, 90

• Marc E. Levitt: Guest Editor's Introduction: Microprocessors Lead the Way in Complex Design. 8-9

• Marc E. Levitt:
  Designing UltraSparc for Testability. 10-17
  

• Lynn Youngs, Siva Paramanandam:
  Mapping and Repairing Embedded-Memory Defects. 18-24
  

• Dilip K. Bhavsar, John H. Edmondson:
  Alpha 21164 Testability Strategy. 25-33
  
• Jainendra Kumar:
  Prototyping the M68060 for Concurrent Verification. 34-41
  
• Margarida F. Jacome, Viktor S. Lapinskii:
  NREC: Risk Assessment and Planning of Complex Designs. 42-49
  

• Robert Wu, Jerry Gerner, Richard Wheelus, Kevin Lew:
  Testing Logic-Intensive Memory ICs on Memory Testers. 50-54
  
• Al Bailey, Tim Lada, Jim Preston:
  Collateral ASIC Test. 55-63
  
• Ghassan Al Hayek, Yves Le Traon, Chantal Robach:
  Impact of System Partitioning on Test Cost. 64-74
  

• Hardware-Software Codesign. 75-83
  

• Panel Summaries. 84-87

• Conference Reports. 88-90

• Design Automation Technical Committee Newsletter. 92-93

• Test Technology Tc Newsletter. 94-95

• Scott Davidson:
  George learns test. 96-
  

Volume 14, Number 2, April-June 1997

• VHDL fault injection questioned. 2-3

• News. 3-

• Ivo Bolsens, Marco Cecchini: IP-based business conflicts. 4, 92

• Adventures in the Mainframe Trade. 5-13
  

• Peter Marwedel, Carlos A. López-Barrio: Guest Editor's Introduction: Design, Design Automation, and Test in Europe. 14-15

• Clifford Liem, François Naçabal, Carlos A. Valderrama, Pierre G. Paulin, Ahmed Amine Jerraya:
  System-on-a-Chip Cosimulation and Compilation. 16-25
  

• Manoj Sachdev:
  Open Defects in CMOS RAM Address Decoders. 26-33
  

• Jean-Michel Karam, Bernard Courtois, Hicham Boutamine:
  CAD Tools for Bridging Microsystems and Foundries. 34-39
  

• Reinaldo A. Bergamaschi, Salil Raje:
  Observable Time Windows: Verifying High-Level Synthesis Results. 40-50
  

• Rolf Drechsler, Bernd Becker, Stefan Ruppertz:
  The K*BMD: A Verification Data Structure. 51-59
  

• Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras:
  Fault-Secure Parity Prediction Arithmetic Operators. 60-71
  

• Rajesh K. Gupta, Stan Y. Liao:
  Using a Programming Language for Digital System Design. 72-80
  

• Testing Embedded Cores. 81-89
  

• Author Guidelines IEEE Design & Test. 90-91

• Design Automation Technical Committee Newsletter. 93-

• Test Technology TC Newsletter. 94-95

• Scott Davidson:
  Why projects are late. 96-
  

Volume 14, Number 3, July-September 1997

• About this super issue. 1-

• News. 6, 122

• Luciano Lavagno, Nanette Collins: DAC 97 Panel: Next-Generation HDLs. 7-8

• Conference Reports. 8-10

• Gadi Singer:
  The Future of Test and DFT. 11-14
  

• Tony Ambler, Magdy S. Abadir: Design and Test Economics-An Extra Dimension. 15-16

• José M. Miranda:
  A BIST and Boundary-Scan Economics Framework. 17-23
  
• James Debardelaben, Vijay K. Madisetti, Anthony J. Gadient:
  Incorporating Cost Modeling in Embedded-System Design. 24-35
  
• Craig T. Pynn:
  Analyzing Manufacturing Test Costs. 36-40
  
• Jon Turino:
  Test Economics in the 21st Century. 41-44
  
• Magdy S. Abadir, Rohit Kapur:
  Cost-Driven Ranking of Memory Elements for Partial Intrusion. 45-50
  
• Des Farren, Anthony P. Ambler:
  The Economics of System-Level Testing. 51-58
  

• Jerry M. Soden, Richard E. Anderson, Christopher L. Henderson:
  IC Failure Analysis: Magic, Mystery, and Science. 59-69
  
• Donald Staab, Eugene R. Hnatek:
  Diagnosing IC Failures in a Fast Environment. 70-75
  
• David P. Vallett:
  IC Failure Analysis: The Importance of Test and Diagnostics. 76-82
  
• Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Kinra, Jayashree Saxena:
  Automated Diagnosis in Testing and Failure Analysis. 83-89
  
• Keith Baker, Jos van Beers:
  Shmoo Plotting: The Black Art of IC Testing. 90-97
  
• Robert C. Aitken:
  Modeling the Unmodelable: Algorithmic Fault Diagnosis. 98-103
  

• Mario Zagar, Danko Basch:
  Microprocessor Architecture Design with ATLAS. 104-112
  
• A D&T Roundtable: Built-In Self-Test for Designers. 113-121

• Design Automation Technical Committee Newsletter. 123-125

• Test Technology Tc Newsletter. 126-127

• Jerry M. Soden, Christopher L. Henderson: Still in the Stone Age? 128-

Volume 14, Number 4, October-December 1997

• D&T to greet new EIC. 1-

• Victor P. Nelson: Which tester is right for your MCM? 4-5

• Conference Reports. 5-6

• Burton J. Smith: Burton Smith's Multithreaded Success Strategy. 7-13

• Yervant Zorian, Rajesh K. Gupta: Design and Test of Core-Based Systems on Chips. 14-

• Rajesh K. Gupta, Yervant Zorian:
  Introducing Core-Based System Design. 15-25
  
• Ann Marie Rincon, Cory Cherichetti, James A. Monzel, David R. Stauffer, Michael T. Trick:
  Core Design and System-on-a-Chip Integration. 26-35
  
• Frank S. Eory:
  A Core-Based System-to-Silicon Design Methodology. 36-41
  
• Vijay K. Madisetti, Lan Shen:
  Interface Design for Core-Based Systems. 42-51
  
• Nur A. Touba, Bahram Pouya:
  Using Partial Isolation Rings to Test Core-Based Designs. 52-59
  
• Mika Kuulusa, Jari Nurmi, Janne Takala, Pasi Ojala, Henrik Herranen:
  A Flexible DSP Core for Embedded Systems. 60-68
  
• Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto, Enrico Macii, Massimo Poncino:
  Testing Core-Based Systems: A Symbolic Methodology. 69-77
  

• Keith A. Jenkins:
  Detecting and Preventing Measurement Errors. 78-86
  
• Al Crouch, Jeff Freeman:
  Designing and Verifying Embedded Microprocessors. 87-94
  
• A D&T Roundtable: What's Next for Microelectronics Education? 95-102

• IEEE Design & Test of Computers: 1997 Annual Index, Volume 14. 103-107

• DDATC Newsletter. 108-109

• Tttc Newsletter. 110-111

• Lee Whetsel: A silicon El Niño? 112-

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