Volume 15, Number 1, January-March 1998

EIC Message

• 
  Yervant Zorian: D&T: 15th Year in Service. 1-

News

• 
  News. 4-5

Conference Reports

• 
  Teruhiko Yamada: 1997 Asian Test Symposium. 6-

Panel Summaries

• 
  Dilip K. Bhavsar, Yervant Zorian: ITC 97 Panel Sessions. 7, 91

Guest Editor's Introduction

• 
  Fabrizio Lombardi: Field-Programmable Gate Arrays. 8-9

Feature

• 
  Vaughn Betz, Jonathan Rose: How Much Logic Should Go in an FPGA Logic Block? 10-15
• 
  Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Silviu M. S. A. Chiricescu, Weidong Xu, Paul M. Zavracky: Rothko: A Three-Dimensional FPGA. 16-23
• 
  Shanzhen Xing, William W. H. Yu: FPGA Adders: Performance Evaluation and Optimal Design. 24-29
• 
  Roger Woods, David W. Trainor, Jean-Paul Heron: Applying an XC6200 to Real-Time Image Processing. 30-38
• 
  Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara: Universal Fault Diagnosis for Lookup Table FPGAs. 39-44
• 
  Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Interconnect of RAM-Based FPGAs. 45-50

Special Feature

• 
  Kenneth L. Shepard, Vinod Narayanan: Conquering Noise in Deep-Submicron Digital ICs. 51-62
• 
  Stefano Barbagallo, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Integrating Online and Offline Testing of a Switching Memory. 63-70
• 
  Felice Balarin, Luciano Lavagno, Praveen K. Murthy, Alberto L. Sangiovanni-Vincentelli: Scheduling for Embedded Real-Time Systems. 71-82
• 
  A D&T Roundtable: Relative Effectiveness of Tests. 83-90

Test Technology TC Newsletter

• 
  Test Technology TC Newsletter. 92-94

Design Automation TC Newsletter

• 
  Design Automation TC Newsletter. 95-

The Last Byte

• 
  Hideo Fujiwara: Needed: Third-generation ATPG Benchmarks. 96-

Volume 15, Number 2, April-June 1998

EIC Message

• 
  Our new world. 1-

Letters

• 
  Letters. 3-

Conference Reports

• 
  Patrick Dewilde: Date 98. 4-

Panel Summaries

• 
  Panel Summaries. 5-7

Feature

• 
  Colin Maunder: The Future: Plug and Pray? 8-13
• 
  Vladimir Székely, Márta Rencz, Bernard Courtois: Tracing the Thermal Behavior of ICs. 14-21
• 
  Kayhan Küçükçakar, Chih-Tung Chen, Jie Gong, Wim Philipsen, Thomas E. Tkacik: Matisse: An Architectural Design Tool for Commodity ICs. 22-33
• 
  Peter J. Ashenden, Philip A. Wilsey, Dale E. Martin: SUAVE: Extending VHDL to Improve Data Modeling Support. 34-44
• 
  Rolf Ernst: Codesign of Embedded Systems: Status and Trends. 45-54
• 
  Yeong-Ruey Shieh, Cheng-Wen Wu: Control and Observation Structures for Analog Circuits. 56-64
• 
  Wen-Jong Fang, Allen C.-H. Wu: Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs. 65-72
• 
  Samvel K. Shoukourian: A Unified Design Methodology for Offline and Online Testing. 73-79
• 
  Yuri V. Malyshenko: Functional Fault Models for Analog Circuits. 80-85
• 
  Meh-Ron Amerian, William D. Atwell Jr., Ian Burgess, Gary D. Fleeman, David Y. Lepejian, T. W. Williams, Farzad Zarrinfar, Yervant Zorian: A D&T Roundtable: Testing Mixed Logic and DRAM Chips. 86-92

DATC Newsletter

• 
  DATC Newsletter. 93-

Test Technology TC Newsletter

• 
  Test Technology TC Newsletter. 94-95

The Last Byte

• 
  Scott Davidson: The Newer Colossus. 96-

Volume 15, Number 3, July-September 1998

Department

• 
  Conference Reports. 2-

From the Editor-in-Chief

• 
  Yervant Zorian: Once Again, a Super Issue. 3-

Keynote

• 
  Wilfred Corrigan: ASIC Challenges: Emerging from a Primordial Soup. 4-7

Feature

• 
  David E. Schimmel, Chryssa Dislis: Guest Editors' Introduction: Early Modeling and Analysis of Packaged Systems. 8-9
• 
  Peter Sandborn, Mike Vertal: Analyzing Packaging Trade-Offs During System Design. 10-19
• 
  Michael Scheffler, Daniel Ammann, Andreas Thiel, Claus M. Habiger, Gerhard Tröster: Modeling and Optimizing the Costs of Electronic Systems. 20-26
• 
  Earl E. Swartzlander Jr.: VLSI, MCM, and WSI: A Design Comparison. 28-34
• 
  Claudio Truzzi: The Role of the Good-Die Project in Miniaturized-System Design. 35-43
• 
  Koppolu Sasidhar, Leon Alkalai, Abhijit Chatterjee: Testing NASA's 3D-Stack MCM Space Flight Computer. 44-55

Microprocessor Testing

• 
  Wayne M. Needham: Guest Editor's Introduction: Microprocessor Testing Today. 56-57
• 
  Jeff Brauch, Jay Fleischman: Design of Cache Test Hardware on the HP PA8500. 58-63
• 
  R. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma: Testability Features of the AMD-K6 Microprocessor. 64-69
• 
  Dale Amason, Alfred L. Crouch, Renny Eisele, Grady Giles, Michael Mateja: Test Development for Second-Generation ColdFire Microprocessors. 70-76
• 
  Adrian Carbine, Derek Feltham: Pentium Pro Processor Design for Test and Debug. 77-82
• 
  Thomas G. Foote, Dale E. Hoffman, William V. Huott, Timothy J. Koprowski, Mary P. Kusko, Bryan J. Robbins: Testing the 500-MHz IBM S/390 Microprocessor. 83-89
• 
  Carol Pyron, Javier Prado, James Golab: Test Strategy for the PowerPC 750 Microprocessor. 90-97
• 
  Carol Stolicny, Richard Davies, Pamela McKernan, Tuyen Truong: Alpha 21164 Manufacturing Test Development and Coverage Analysis. 98-104

Special Feature

• 
  Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Effective Built-In Self-Test for Booth Multipliers. 105-111
• 
  Michel Dubois, Jaeheon Jeong, Yong Ho Song, Adrian Moga: Rapid Hardware Prototyping on RPM-2. 112-118
• 
  A D&T Roundtable: Challenges for Low-Power and High-Performance Chips. 119-124

Department

• 
  Test Technology TC Newsletter. 125-126
• 
  Design Automation Technical Committee Newsletter. 126-127

The Last Byte

• 
  Scott Davidson: Minutes Found on a Cave Wall. 128-

Volume 15, Number 4, October-December 1998

EIC Message

• 
  Yervant Zorian: Challenges and Options. 3-

Standards

• 
  Mukund Modi: IEEE Standards Coordinating Committee 20. 4-6

Keynote

• 
  Bill Bottoms: The Third Millennium's Test Dilemma. 7-11

Feature

• 
  Ramesh Karri, Michael Nicolaidis: Guest Editors' Introduction: Online VLSI Testing. 12-16
• 
  Hussain Al-Asaad, Brian T. Murray, John P. Hayes: Online BIST for Embedded Systems. 17-24
• 
  Samuel Norman Hamilton, Alex Orailoglu: Efficient Self-Recovering ASIC Design. 25-35
• 
  Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig: Synthesizing Fast, Online-Testable Control Units. 36-41
• 
  Cecilia Metra, Michele Favalli, Bruno Riccò: Concurrent Checking of Clock Signal Correctness. 42-48
• 
  Jien-Chung Lo: Online Current Testing. 49-56
• 
  Eberhard Böhl, Thomas Lindenkreuz, Matthias Meerwein: On-Chip IDDQ Testing in the AE11 Fail-Stop Controller. 57-65
• 
  Cristiana Bolchini, Fabio Salice, Donatella Sciuto: Fault Analysis for Networks with Concurrent Error Detection. 66-74

Special Feature

• 
  Glenn H. Chapman, Benoit Dufort: Using Laser Defect Avoidance to Build Large-Area FPGAs. 75-81

A D&T Roundtable

• 
  Deep-Submicron Noise. 82-88

IEEE Design & Test of Computers 1998 Annual Index, Volume 15

• 
  IEEE Design & Test of Computers, 1998 Annual Index, Volume 15. 89-92

Test Technology TC Newsletter

• 
  TTTC Newsletter. 93-94

Design Automation TC Newsletter

• 
  Design Automation Technical Committee Newsletter. 95-

The Last Byte

• 
  Scott Davidson: The Last Byte. 96-