Volume 13,
Number 1,
August 1998
- Vishwani D. Agrawal:
Editorial.
5
- Nihal J. Godambe, C.-J. Richard Shi:
Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS.
7-17
- Chau-Shen Chen, TingTing Hwang:
Layout Driven Selection and Chaining of Partial Scan Flip-Flops.
19-27
- Sebastian T. J. Fenn, Michael Gössel, Mohammed Benaissa, David Taylor:
On-Line Error Detection for Bit-Serial Multipliers in GF(2m).
29-40
- Jacob Savir:
On-Chip Weighted Random Patterns.
41-50
- Yinghua Min, Zhongcheng Li:
IDDT Testing versus IDDQ Testing.
51-55
- Kim T. Le, Kewal K. Saluja:
A Heuristic Measure to Maximize Detected Faults per Test.
57-60
- Antonis M. Paschalis, Nikolaos Gaitanis, Dimitris Gizopoulos, Panagiotis Kostarakis:
A Totally Self-Checking 1-out-of-3 Code Error Indicator.
61-66
Volume 13,
Number 2,
October 1998
- Vishwani D. Agrawal:
Editorial.
75
- Niraj K. Jha:
Guest Editorial.
77
- Sujit Dey, Anand Raghunathan, Kenneth D. Wagner:
Design for Testability Techniques at the Behavioral and Register-Transfer Levels.
79-91
- Frank F. Hsu, Janak H. Patel:
High-Level Controllability and Observability Analysis for Test Synthesis.
93-103
- Yiorgos Makris, Alex Orailoglu:
RTL Test Justification and Propagation Analysis for Modular Designs.
105-120
- Li-C. Wang, Magdy S. Abadir:
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays.
121-135
- Jian Shen, Jacob A. Abraham:
Synthesis of Native Mode Self-Test Programs.
137-148
- Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Allocation Techniques for Reducing BIST Area Overhead of Data Paths.
149-166
- Christos A. Papachristou, Mikhail Baklashov, Kowen Lai:
High-Level Test Synthesis for Behavioral and Structural Designs.
167-188
- Nilanjan Mukherjee, Ramesh Karri:
Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures.
189-200
- Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.
201-212
Volume 13,
Number 3,
December 1998
Copyright © Wed Dec 23 21:51:17 2009
by Michael Ley (ley@uni-trier.de)
