Journal of Electronic Testing, Volume 2

Volume 2, Number 1, March 1991

• R. G. Bennetts, A. Osseyran:
  IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status. 11-25
  
• C. M. Maunder, Rodham E. Tulloss:
  An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1. 27-42
  
• Kenneth P. Parker, Stig Oresjo:
  A language for describing boundary scan devices. 43-75
  
• Frans Jong, José S. Matos, José M. Ferreira:
  Boundary scan test, test methodology, and fault modeling. 77-88
  
• Don Sterba, Andy Halliday, Don McClean:
  ATPG and diagnostics for boards implementing boundary scan. 89-98
  
• Matthew L. Fichtenbaum, Gordon D. Robinson:
  Scan test architectures for digital board testers. 99-105
  
• Bulent I. Dervisoglu:
  Features of a Scan and Clock Resource chip for providing access to board-level test functions. 107-115
  
• Jung-Cheun Lien, Melvin A. Breuer:
  An optimal scheduling algorithm for testing interconnect using boundary scan. 117-130
  

Volume 2, Number 2, June 1991

• Sumit Ghosh, Tapan J. Chakraborty:
  On behavior fault modeling for digital designs. 135-151
  
• Geetani Edirisooriya, John P. Robinson:
  Cyclic code weight spectra and BIST aliasing. 153-163
  
• Kwanghyun Kim, Joseph G. Tront, Dong Sam Ha:
  BIDES: A BIST design expert system. 165-179
  
• Michele Favalli, Piero Olivo, Bruno Riccò, Fabio Somenzi:
  Fault simulation for general FCMOS ICs. 181-190
  
• Wilfried Daehn:
  Fault simulation using small fault samples. 191-203
  
• Kanji Hirabayashi:
  Self-checking CMOS circuits using pass-transistor logic. 205-208
  

Volume 2, Number 3, August 1991

• Bjørg Reppen, Einar J. Aas:
  Combined probabilistic testability calculation and compact test generation for PLAs. 215-227
  
• Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch:
  Fault modeling and fault equivalence in CMOS technology. 229-241
  
• Don E. Ross, Kenneth M. Butler, M. Ray Mercer:
  Exact ordered binary decision diagram size when representing classes of symmetric functions. 243-259
  
• Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh:
  A methodology for the design of SFS/SCD circuits for a class of unordered codes. 261-277
  
• P. K. Lui, Jon C. Muzio:
  Constrained parity testing. 279-291
  
• Bruno Ciciani:
  Redundancy effect on yield of binary tree RAMs. 293-306
  
• R. Kh. Latypov:
  Comments on "optimizing error masking in BIST by output data modification". 307-308
  

Volume 2, Number 4, November 1991

• George Markowsky:
  Bounding fault detection probabilities in combinational circuits. 315-323
  
• Warren H. Debany Jr., Carlos R. P. Hartmann:
  Bounds on the sizes of irredundant test sets and sequences for combinational logic networks. 325-338
  
• Irith Pomeranz, Zvi Kohavi:
  The minimum test set problem for circuits with nonreconvergent fanout. 339-349
  
• Abhijit Chatterjee, Jacob A. Abraham:
  Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling. 351-372
  
• Wen-Ben Jone, Anita Gleason:
  Analysis of Hamming count compaction scheme. 373-384
  
• Meryem Marzouki:
  Model-based reasoning for electron-beam debugging of VLSI circuits. 385-394
  
• Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
  Checkpoints in irredundant two-level combinational circuits. 395-397