Journal of Electronic Testing, Volume 28

Volume 28, Number 1, February 2012

• Vishwani D. Agrawal:
  Editorial. 1
  
• Erik Jan Marinissen, Yervant Zorian:
  Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits. 13-14
  
• Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen:
  Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost. 15-25
  
• Yi Lou, Zhuo Yan, Fan Zhang, Paul D. Franzon:
  Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods. 27-38
  
• Sukeshwar Kannan, Bruce C. Kim, Byoungchul Ahn:
  Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects. 39-51
  
• Benjamin Backes, Colin McDonough, Larry Smith, Wei Wang, Robert E. Geer:
  Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits. 53-62
  
• Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy, Henrik Hovsepyan, Ara Markosian, Ehrenfried Zschech, Rene Huebner:
  Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance. 63-72
  
• Erik Jan Marinissen, Chun-Chuan Chi, Mario H. Konijnenburg, Jouke Verbree:
  A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper. 73-92
  
• Michael Buttrick, Sandip Kundu:
  On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs. 93-101
  
• Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen:
  Optimization Methods for Post-Bond Testing of 3D Stacked ICs. 103-120
  
• Breeta SenGupta, Urban Ingelsson, Erik Larsson:
  Scheduling Tests for 3D Stacked Chips under Power Constraints. 121-135
  
• Vladimir Pasca, Lorena Anghel, Michael Nicolaidis, Mounir Benabdenbi:
  CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems. 137-150
  

Volume 28, Number 2, April 2012

• Vishwani D. Agrawal:
  Editorial. 151-152
  
• Test Technology Newsletter. 153-154
  
• Xiaomei Chen, Xiaofeng Meng, Guohua Wang:
  A Modified Simulation-Based Multi-Signal Modeling for Electronic System. 155-165
  
• R. M. Ayadi, S. Mahresi, M. Masmoudi:
  Self-Calibration of Output Match and Reverse Isolation in LNAs Based Switchable Resistor. 167-176
  
• Mohammed Ashfaq Shukoor, Vishwani D. Agrawal:
  Diagnostic Test Set Minimization and Full-Response Fault Dictionary. 177-187
  
• Michelangelo Grosso, Wilson Javier Perez Holguin, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda, J. Velasco Medina:
  Software-Based Testing for System Peripherals. 189-200
  
• Junxia Ma, Mohammad Tehranipoor, Patrick Girard:
  A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk. 201-214
  
• Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
  Analysis and Fault Modeling of Actual Resistive Defects in ATMEL [InlineMediaObject not available: see fulltext.] eFlash Memories. 215-228
  
• Claude Thibeault, Yassine Hariri, C. Hobeika:
  Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors. 229-242
  
• Yang Zhao, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
  Testing of Low-cost Digital Microfluidic Biochips with Non-Regular Array Layouts. 243-255
  
• Ashok Kavithamani, Venugopal Manikandan, Nanjundappan Devarajan:
  Fault Detection of Analog Circuits Using Network Parameters. 257-261
  

Volume 28, Number 3, June 2012

• Vishwani D. Agrawal:
  Editorial. 263-264
  
• Test Technology Newsletter. 265-266
  
• Hsin-Wen Ting:
  Digital-Compatible Testing Scheme for Operational Amplifier. 267-277
  
• Hui Luo, Youren Wang, Hua Lin, Yuanyuan Jiang:
  A New Optimal Test Node Selection Method for Analog Circuit. 279-290
  
• Bing Long, Shulin Tian, Houjun Wang:
  Diagnostics of Filtered Analog Circuits with Tolerance Based on LS-SVM Using Frequency Features. 291-300
  
• Ireneusz Mrozek, Vyacheslav N. Yarmolik:
  Iterative Antirandom Testing. 301-315
  
• Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
  Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. 317-329
  
• K. Castellani-Coulié, Hassen Aziza, Gilles Micolau, Jean Michel Portal:
  Optimization of SEU Simulations for SRAM Cells Reliability under Radiation. 331-338
  
• S. Ben Dhia, Alexandre Boyer, Bertrand Vrignon, Mikaël Deobarro:
  IC Immunity Modeling Process Validation Using On-Chip Measurements. 339-348
  
• Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera:
  NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. 349-363
  
• Stefan R. Vock, Omar Escalona, Colin Turner, Frank J. Owens:
  Challenges for Semiconductor Test Engineering: A Review Paper. 365-374
  
• Joonhwan Yi, John P. Hayes:
  Robust Coupling Delay Test Sets. 375-388
  

Volume 28, Number 4, August 2012

• Vishwani D. Agrawal:
  Editorial. 389-390
  
• Test Technology Newsletter. 391-392
  
• Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido Gronthoud:
  ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus. 393-404
  
• Shreyas Sen, Aritra Banerjee, Vishwanath Natarajan, Shyam Kumar Devarakond, Hyun Woo Choi, Abhijit Chatterjee:
  BIST/Digital-Compatible Testing of RF Devices Using Distortion Model Fitting. 405-419
  
• Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira:
  Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits. 421-434
  
• Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar:
  On the Reuse of TLM Mutation Analysis at RTL. 435-448
  
• Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti:
  Cohesive Coverage Management: Simulation Meets Formal Methods. 449-468
  
• Viacheslav Izosimov, Giuseppe Di Guglielmo, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Masahiro Fujita:
  Time-Constraint-Aware Optimization of Assertions in Embedded Software. 469-486
  
• Michal Tadeusiewicz, Stanislaw Halgas:
  Multiple Soft Fault Diagnosis of Nonlinear Circuits Using the Continuation Method. 487-493
  
• Nicola Bombieri, Franco Fummi, Valerio Guarnieri:
  FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction. 495-510
  
• Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara:
  Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. 511-521
  
• Mottaqiallah Taouil, Said Hamdioui:
  Yield Improvement for 3D Wafer-to-Wafer Stacked Memories. 523-534
  
• Badar-ud-din Ahmed, Youren Wang, Rizwan Ullah, Najam-ud-din Ahmed:
  A Novel TOPSIS-Based Test Vector Compaction Technique for Analog Fault Detection. 535-540
  
• Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
  Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. 541-549
  

Volume 28, Number 5, October 2012

• Vishwani D. Agrawal:
  Editorial. 551-552
  
• Test Technology Newsletter. 553-554
  
• Hsiu-Ming (Sherman) Chang, David C. Keezer:
  Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing. 555-556
  
• Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham:
  Built-in Self Test of RF Subsystems with Integrated Detectors. 557-569
  
• Shao-Feng Hung, Hao-Chiao Hong:
  Experimental Results of Testing a BIST Σ-Δ ADC on the HOY Wireless Test Platform. 571-584
  
• Hyunjin Kim, Jacob A. Abraham:
  A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement. 585-597
  
• Elie H. Sarraf, Ankit Kansal, Mrigank Sharma, Edmond Cretu:
  FPGA-based Novel Adaptive Scheme Using PN Sequences for Self-Calibration and Self-Testing of MEMS-based Inertial Sensors. 599-614
  
• Jingbo Duan, Bharath K. Vasan, Chen Zhao, Degang Chen, Randall L. Geiger:
  On Chip Signal Generators for Low Overhead ADC BIST. 615-623
  
• Tsung-Yen Tsai, Sadok Aouini, Gordon W. Roberts:
  High Speed On-Chip Signal Generation for Debug and Diagnosis. 625-640
  
• Kazuyuki Wakabayashi, Keisuke Kato, Takafumi Yamada, Osamu Kobayashi, Haruo Kobayashi, Fumitaka Abe, Kiichi Niitsu:
  Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator. 641-651
  
• Kemal Kulovic, Martin Margala:
  Time-Based Embedded Test Instrument with Concurrent Voltage Measurement Capability. 653-671
  
• Samed Maltabas, Kemal Kulovic, Martin Margala:
  Novel Practical Built-in Current Sensors. 673-683
  
• Didac Gómez, Josep Altet, Diego Mateo:
  On the Use of Static Temperature Measurements as Process Variation Observable. 685-695
  
• Sachin Dileep Dasnurkar, Jacob A. Abraham:
  Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing. 697-704
  
• Xuan-Lun Huang, Jiun-Lang Huang, Hung-I Chen, Chang-Yu Chen, Tseng Kuo-Tsai, Ming-Feng Huang, Yung-Fa Chou, Ding-Ming Kwai:
  An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. 705-722
  
• Mozar Naing, Dallas Webster, Nolan Blue, Rick Hudgens, Zahir Parkar, Sumeer Bhatara, Pankaj Gupta, Donald Y. C. Lie:
  Maximizing Parallel Testing in an FM Receiver. 723-731
  
• Minshun Wu, Degang Chen, Jingbo Duan:
  An Accurate and Cost-Effective Jitter Measurement Technique Using a Single Test Frequency. 733-743
  
• Bing Long, Shulin Tian, Houjun Wang:
  Feature Vector Selection Method Using Mahalanobis Distance for Diagnostics of Analog Circuits Based on LS-SVM. 745-755
  
• Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
  Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. 757-771
  

Volume 28, Number 6, December 2012

• Vishwani D. Agrawal:
  Editorial. 773-774
  
• Test Technology Newsletter. 775-776
  
• Marta Portela-Garcia, Almudena Lindoso, Luis Entrena, Mario García-Valderas, Celia López-Ongil, N. Marroni, Bernardo Pianta, Letícia Maria Bolzani Poehls, Fabian Vargas:
  Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach. 777-789
  
• Alexandre Boyer, S. Ben Dhia, B. Li, C. Lemoine, Bertrand Vrignon:
  Prediction of Long-term Immunity of a Phase-Locked Loop. 791-802
  
• Juliano Benfica, Letícia Maria Bolzani Poehls, Fabian Vargas, José Lipovetzky, Ariel Lutenberg, Edmundo Gatti, Fernando Hernandez:
  A Test Platform for Dependability Analysis of SoCs Exposed to EMI and Radiation. 803-816
  
• Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi:
  Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis. 817-829
  
• Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich:
  Structural Test and Diagnosis for Graceful Degradation of NoC Switches. 831-841
  
• Stelios Neophytou, Kyriakos Christou, Maria K. Michael:
  A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits. 843-856
  
• Jari Hannu, Juha Häkkinen, Juha-Veikko Voutilainen, Heli Jantunen, Markku Moilanen:
  Current State of the Mixed-Signal Test Bus 1149.4. 857-863
  
• J. M. Ruiz, Raúl Fernández-Garcia, I. Gil, M. Morata:
  Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout. 865-868
  
• Kanad Chakraborty, Vishwani D. Agrawal:
  Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®. 869-875
  
• Yi Ren, L. Fan, Li Chen, Shi-Jie Wen, Richard Wong, N. W. van Vonno, Arthur F. Witulski, Bharat L. Bhuva:
  Single-Event Effects Analysis of a Pulse Width Modulator IC in a DC/DC Converter. 877-883
  

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