Journal of Electronic Testing, Volume 4

Volume 4, Number 1, February 1993

Vishwani D. Agrawal:
Editorial. 5
Srinivas Devadas, Petra Michel:
Guest editorial. 7
Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
An approach to sequential circuit diagnosis based on formal verification techniques. 11-17
Hyunwoo Cho, Seh-Woong Jeong, Fabio Somenzi, Carl Pixley:
Synchronizing sequences and symbolic traversal techniques in test generation. 19-31
Margot Karam, Gabriele Saucier:
Functional versus random test generation for sequential circuits. 33-41
Johannes Steensma, Werner Geurts, Francky Catthoor, Hugo De Man:
Testability analysis in high level data path synthesis. 43-56
Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal:
Finite state machine synthesis with fault tolerant test function. 57-69
Sen-Pin Lin, Charles Njinda, Melvin A. Breuer:
Generating a family of testable designs using the BILBO methodology. 71-89
Srinivas Devadas, Kurt Keutzer, Sharad Malik:
A synthesis-based test generation and compaction algorithm for multifaults. 91-104
Bernhard Eschermann:
Enhancing on-line testability during synthesis. 105-116

Vishwani D. Agrawal:
Editorial. 123
Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya:
Logical redundancies in irredundant combinational circuits. 125-130
Kanji Hirabayashi:
Delay fault simulation of sequential circuits. 131-135
Jaushin Lee, Janak H. Patel:
An architectural level test generator based on nonlinear equation solving. 137-150
Geetani Edirisooriya, John P. Robinson:
Aliasing properties of circular MISRs. 151-158
Jung-Cheun Lien, Melvin A. Breuer:
Test program synthesis for modules and chips having boundary scan. 159-180
Nazar S. Haider, Nick Kanopoulos:
Efficient board interconnect testing using the split boundary scan register. 181-189
Mark A. Heap:
On the exact ordered binary decision diagram size of totally symmetric functions. 191-195

Vishwani D. Agrawal:
Editorial. 199
Charles E. Stroud, Ahmed E. Barbour:
Testability and test generation for majority voting fault-tolerant circuits. 201-214
Chao Feng, Jon C. Muzio, Fabrizio Lombardi:
On the testability of array structures for FFT computation. 215-224
Zaifu Zhang, Robert D. McLeod, Witold Pedrycz:
A neural network algorithm for testing stuck-open faults in CMOS combinational circuits. 225-235
El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny:
On the generation of test patterns for multiple faults. 237-253
Byung S. So, Charles R. Kime:
A fault simulation method: Parallel pattern critical path tracing. 255-265
Egor S. Sogomonyan, Michael Gössel:
Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs. 267-281
Ye. L. Stolov:
Testing of multi-output circuits by means of signature analyzer. 283
Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
The optimistic update theorem for path delay testing in sequential circuits. 285-290

Vishwani D. Agrawal:
Editorial. 295
Mani Soma:
Guest editor's introduction. 297-298
José Luis Huertas, Adoración Rueda, Diego Vázquez:
Improving the testability of switched-capacitor filters. 299-313
Franc Novak, Igor Mozetic, Marina Santo Zarnik, Anton Biasizzo:
Enhancing design-for-test for active analog filters by using CLP. 315-329
Naim Ben Hamida, Bozena Kaminska:
Multiple fault analog circuit testing by sensitivity analysis. 331-343
Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
Fault simulation of linear analog circuits. 345-360
Nai-Chi Lee:
A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards. 361-368
B. R. Wilkins, B. S. Suparjo:
A structure for interconnect testing on mixed-signal boards. 369-374

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