Integration, Volume 21

Volume 21, Number 1-2, November 1996

• Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden:
  Performance optimization of VLSI interconnect layout. 1-94
  
• Emil Gizdarski:
  Built-in self-test for folded bit-line Mbit DRAMs. 95-112
  
• Petru Eles, Krzysztof Kuchcinski, Zebo Peng:
  Synthesis of systems specified as interacting VHDL processes. 113-138
  

Volume 21, Number 3, December 1996

• Alexandre Yakovlev, Albert Koelmans, Alexei L. Semenov, D. J. Kinniment:
  Modelling, analysis and synthesis of asynchronous control circuits using Petri nets. 143-170
  
• Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
  A three-layer over-the-cell multi-channel router for a new cell model. 171-189
  
• Asad A. Ismaeel, Muhammad K. Dhodhi, Rajan Mathew:
  Assignment and allocation of highly testable data paths under scan optimization. 191-207
  
• Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis:
  Testing CMOS combinational iterative logic arrays for realistic faults. 209-228
  

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