Integration, Volume 36

Volume 36, Number 1-2, September 2003

• Ahmad A. Hiasat, Omar Hasan:
  Bit-serial architecture for rank order and stack filters. 3-12
  
• Ahmad A. Hiasat:
  An arithmetic residue to binary conversion technique. 13-25
  
• Dimitri Kagaris:
  On minimum delay clustering without replication. 27-39
  
• Sanjay Sharma, Sanjay Attri, R. C. Chauhan:
  Low-power VLSI synthesis of DSP systems. 41-54
  
• Xianyang Jiang, Xubang Shen, Tianxu Zhang, Huayu Liu:
  An improved circuit-partitioning algorithm based on min-cut equivalence relation. 55-68
  
• Shahar Bar-Or, Guy Even, Yariv Levin:
  Generation of representative input vectors for parametric designs: from low precision to high precision. 69-82
  
• J. A. Sainz, A. Rubio:
  Adaptable I/O pad circuit for multiple voltage units bus operation. 83-86
  

Volume 36, Number 3, October 2003

• A. Srivastava, H. N. Venkata:
  Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETS. 87-101
  
• Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
  Synthesis of integer multipliers in sum of pseudoproducts form. 103-119
  
• Angus Wu, Peter W. M. Tsang, Johnson Tang:
  FPGA implementation of a near computation free image compression scheme based on adaptive decimation. 121-143
  
• Haytham Azmi, Hamed Elsimary, M. Ibrahim Youssef, Ahmad Safwat:
  FPGA based multi-standard configurable FSK demodulator. 145-154
  
• Ramesh Chidambaram, V. Sai Prithvi, V. Vaidehi:
  Erratum to "VLSI based fuzzy logic controller enabled adaptive interactive multiple model for target tracking" [Integration 35 (2003) 1-10]. 155
  

Volume 36, Number 4, November 2003

• Francisco V. Fernández:
  Analog and mixed-signal IC design and design methodologies. 157-159
  
• Juan M. Carrillo, J. Francisco Duque-Carrillo, Guido Torelli, José L. Ausín:
  1-V quasi constant-gm input/output rail-to-rail CMOS op-amp. 161-174
  
• Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei:
  Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications. 175-189
  
• Massimo Alioto, Rosario Mita, Gaetano Palumbo:
  Performance evaluation of the low-voltage CML D-latch topology. 191-209
  
• Patrick Quinn, Maxim Pribytko:
  Capacitor matching insensitive algorithmic ADC requiring no calibrations. 211-228
  
• Oscar Guerra, Carlos M. Domínguez-Matas, Sara Escalera, José M. García-González, Gustavo Liñán, Rocio del Río, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez:
  A modem in CMOS technology for data communication on the low-voltage power line. 229-236
  
• Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi:
  IPRAIL - intellectual property reuse-based analog IC layout automation. 237-262