Integration, Volume 38
Volume 38, Number 1, October 2004
Luca Benini: Guest Editorial. 1-2- Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen: A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. 3-17
- Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Cost considerations in network on chip. 19-42
- Pasi Liljeberg, Juha Plosila, Jouni Isoaho: Self-timed communication platform for implementing high-performance systems-on-chip. 43-67
- Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost: HERMES: an infrastructure for low area overhead packet-switching networks on chip. 69-93
- David A. Sigüenza-Tortosa, Tapani Ahonen, Jari Nurmi: Issues in the development of a practical NoC: the Proteo concept. 95-105
- Théodore Marescaux, Vincent Nollet, Jean-Yves Mignolet, Andrei Bartic, W. Moffat, Prabhat Avasare, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins: Run-time support for heterogeneous multitasking on reconfigurable SoCs. 107-130
Volume 38, Number 2, December 2004
- Matthias Gries: Methods for evaluating and covering the design space during early design development. 131-183
- Martin Margala, Hongfan Wang: New approach to design for reusability of arithmetic cores in systems-on-chip. 185-203
- Magdy A. El-Moursy, Eby G. Friedman: Optimum wire sizing of RLC interconnect with repeaters . 205-225
- Falk Roewer, Ulrich Kleine, Klaus-Eberhard Salzwedel, Felix Mednikov, Chhrisitan Pfaffinger, Martin Sellen: A programmable inductive position sensor interface circuit. 227-243
- Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang: A clustering- and probability-based approach for time-multiplexed FPGA partitioning. 245-265
- Soumen Maity, Amiya Nayak, Bimal K. Roy: On characterization of catastrophic faults in two-dimensional VLSI arrays. 267-281
- Abdoul Rjoub, Odysseas G. Koufopavlou: Multithreshold voltage low-swing/low-voltage techniques in logic gates. 283-298
- Ali Ziya Alkar, Remziye Sönmez: A hardware version of the RSA using the Montgomery's algorithm with systolic arrays. 299-307
- Robertas Damasevicius, Vytautas Stuikys: Application of the object-oriented principles for hardware and embedded system design. 309-339
Volume 38, Number 3, January 2005
- Sankar Barua, Joan Carletta, Kishore A. Kotteri, Amy E. Bell: An efficient architecture for lifting-based two-dimensional discrete wavelet transforms. 341-352
- Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha: Quality-of-service and error control techniques for mesh-based network-on-chip architectures. 353-382
- Zhiyuan Yan, Dilip V. Sarwate, Zhongzhi Liu: High-speed systolic architectures for finite field inversion. 383-398
- Hassan Hassan, Mohab Anis, Mohamed I. Elmasry: Design and optimization of MOS current mode logic for parameter variations. 417-437
- Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi: Equidistance routing in high-speed VLSI layout design. 439-449
- Shalini Ghosh, F. Joel Ferguson: Detection probabilities of interconnect breaks: an analysis. 451-465
- Franco Fummi, Cristina Marconcini, Graziano Pravadelli: Logic-level mapping of high-level faults. 467-490
- Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky: Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies. 491-504
- Davood Shahrjerdi, Bahman Hekmatshoar, Ali Khaki-Firooz, Ali Afzali-Kusha: Optimization of the VT control method for low-power ultra-thin double-gate SOI logic circuits. 505-513
- Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon: Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach. 515-524
- Jong-Ru Guo, Chao You, Kuan Zhou, Michael Chu, Peter F. Curran, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald: A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC. 525-540
- Ramprasad Ravichandran, Sung Kyu Lim, Michael T. Niemier: Automatic cell placement for quantum-dot cellular automata. 541-548
Volume 38, Number 4, April 2005
- Wen-Tsong Shiue: Novel state minimization and state assignment in finite state machine design for low-power portable devices. 549-570
- Yeun-Renn Ting, Erl-Huei Lu, Ya-Cheng Lu: Ringed bit-parallel systolic multipliers over a class of fields GF(2m). 571-578
- Ashok K. Srivastava, Srinivas Rao Aluri, Anand Kumar Chamakura: A simple built-in current sensor for IDDQ testing of CMOS data converters. 579-596
- Arda Yurdakul: Multiplierless implementation of 2-D FIR filters. 597-613
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last updated on 2013-06-18T211851 by the dblp team