Integration, Volume 42

Volume 42, Number 1, January 2009

• R. Castro-López, D. Rodríguez de Llera, M. Ismail, Francisco V. Fernández:
  AMS/RF-CMOS circuit design for wireless transceivers. 1-2
  
• James Wilson, Mohammed Ismail:
  Input match and load tank digital calibration of an inductively degenerated CMOS LNA. 3-9
  
• Ewout Martens, Georges G. E. Gielen:
  ANTIGONE: Top-down creation of analog-to-digital converter architectures. 10-23
  
• Jokin Segundo, Luis Quintanilla, Jesús Arias, Lourdes Enríquez, Jesús M. Hernández, José Vicente:
  A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter. 24-33
  
• Artur Silva, Jorge Guilherme, Nuno Horta:
  Reconfigurable multi-mode sigma-delta modulator for 4G mobile terminals. 34-46
  
• Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni:
  A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design. 47-60
  
• Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten:
  Nyquist-criterion based design of a CT SigmaDelta-ADC with a reduced number of comparators. 61-67
  
• Ali Naderi, Mohamad Sawan, Yvon Savaria:
  A low-power 2GHz data conversion using delta modulation for portable application. 68-76
  
• Héctor Solar, Roc Berenguer, Joaquín de No, Iñaki Gurutzeaga, Unai Alvarado, Jon Legarda:
  A fully integrated 23.2dBm P_1dB CMOS power amplifier for the IEEE 802.11a with 29% PAE. 77-82
  
• Fadi Riad Shahroury, Chung-Yu Wu:
  A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network. 83-88
  
• Lars Aspemyr, Henrik Sjöland:
  Third-order nonlinearity vs. load impedance for CMOS low-noise amplifiers. 89-94
  
• Eugeni García-Moreno, Kay Suenaga, Rodrigo Picos, Sebastià A. Bota, Miquel Roca, Eugeni Isern:
  Predictive test strategy for CMOS RF mixers. 95-102
  

Volume 42, Number 2, February 2009

• Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny:
  QNoC asynchronous router. 103-115
  
• Ying Wei, Alex Doboli:
  Reconfigurable DeltaSigma modulator topology design through hierarchical mapping and constraint extraction. 116-127
  
• Juan Antonio Maestro, Pedro Reviriego, Pilar Reyes, Oscar Ruano:
  Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study. 128-136
  
• Bo Liu, Yan Wang, Zhiping Yu, Leibo Liu, Miao Li, Zheng Wang, Jing Lu, Francisco V. Fernández:
  Analog circuit optimization system based on hybrid evolutionary algorithms. 137-148
  
• Haridimos T. Vergos, Costas Efstathiou:
  Efficient modulo 2ⁿ+1 adder architectures. 149-157
  
• Ning Mi, Sheldon X.-D. Tan, Boyuan Yan:
  Multiple block structure-preserving reduced order modeling of interconnect circuits. 158-168
  
• Juan Pablo Alegre, Santiago Celma, Jose Maria Garcia del Pozo, Nicolás J. Medrano-Marqués:
  Fast-response low-ripple envelope follower. 169-174
  
• Haixia Yan, Qiang Zhou, Xianlong Hong:
  Thermal aware placement in 3D ICs using quadratic uniformity modeling approach. 175-180
  
• Selçuk Talay, Engin Deniz Diktas, Günhan Dündar:
  A Sigma-Delta ADC design automation tool with embedded performance estimator. 181-192
  
• Duo Li, Sheldon X.-D. Tan, Lifeng Wu:
  Hierarchical Krylov subspace based reduction of large interconnects. 193-202
  
• Akash Agrawal, Prosenjit Gupta:
  Incremental analysis of large VLSI Layouts. 203-216
  
• George N. Selimis, Apostolos P. Fournaris, Harris E. Michail, Odysseas G. Koufopavlou:
  Improved throughput bit-serial multiplier for GF(2^m) fields. 217-226
  
• Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Katalin Popovici, Xavier Guerin, Ahmed Amine Jerraya, Kai Huang, Lei Li, Xiaolang Yan:
  Simulink^®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation. 227-245
  
• Chiu-Wing Sham, Evangeline F. Y. Young:
  Block flipping and white space distribution for wirelength minimization. 246-253
  
• Toshihiko Yamasaki, Tomoyuki Nakayama, Tadashi Shibata:
  A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter. 254-261
  
• Jarrod A. Roy, Aaron N. Ng, Rajat Aggarwal, Venky Ramachandran, Igor L. Markov:
  Solving modern mixed-size placement instances. 262-275
  

Volume 42, Number 3, June 2009

• Mariano Jiménez-Fuentes, Ramón González Carvajal, Lucía Acosta, Carlos Rubia-Marcos, Antonio J. López-Martín, Jaime Ramírez-Angulo:
  A tunable highly linear CMOS transconductor with 80 dB of SFDR. 277-285
  
• Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras:
  Delay caused by resistive opens in interconnecting lines. 286-293
  
• María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, José M. Mendías:
  Performance-driven scheduling of behavioural specifications. 294-303
  
• Tomás Carrasco Carrillo, José Gabriel Macias-Montero, Aitor Osorio Martí, Javier Sieiro Córdoba, José María Lopez-Villegas:
  CMOS single-ended-to-differential low-noise amplifier. 304-311
  
• Seyed-Abdollah Aftabjahani, Linda S. Milor:
  Timing analysis with compact variation-aware standard cell models. 312-320
  
• J. Mendizabal, Unai Alvarado, I. Guruceaga, Héctor Solar, A. Garcia-Alonso, Roc Berenguer:
  A dual front-end for the new GPS/GALILEO generation in a 0.35 µm SiGe process. 321-331
  

• David Haley, Vincent C. Gaudet, Chris Winstead, Alex J. Grant, Christian Schlegel:
  A dual-function mixed-signal circuit for LDPC encoding/decoding. 332-339
  
• Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong:
  An MTCMOS technology for low-power physical design. 340-345
  
• Silvia Franchini, Antonio Gentile, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile:
  An embedded, FPGA-based computer graphics coprocessor with native geometric algebra support. 346-355
  
• Omar S. Elkeelany:
  On chip novel video streaming system for bi-network multicasting protocols. 356-366
  
• Rostislav (Reuven) Dobkin, Ran Ginosar:
  Two-phase synchronization with sub-cycle latency. 367-375
  
• Saurabh Chaudhury, Krishna Teja Sistla, Santanu Chattopadhyay:
  Genetic algorithm-based FSM synthesis with area-power trade-offs. 376-384
  
• José M. Solana:
  Reducing test application time, test data volume and test power through Virtual Chain Partition. 385-399
  
• Tsung-Yi Ho:
  PIXAR: A performance-driven X-architecture router based on a novel multilevel framework. 400-408
  

• Cristiano Forzan, Davide Pandini:
  Statistical static timing analysis: A survey. 409-435
  

Volume 42, Number 4, September 2009

• Nishith N. Desai, Jonathan R. Haigh, Lawrence T. Clark:
  Reducing process variation impact on replica-timed static random access memory sense timing. 437-448
  
• Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu:
  Handling routability in floorplan design with twin binary trees. 449-456
  
• Keivan Navi, Mehrdad Maeen, Vahid Foroutan, Somayeh Timarchi, Omid Kavehie:
  A novel low-power full-adder cell for low voltage. 457-467
  
• Amir Moradi, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani, Thomas Eisenbarth:
  Vulnerability modeling of cryptographic hardware to power analysis attacks. 468-478
  
• Seung Eun Lee, Nader Bagherzadeh:
  A variable frequency link for a power-aware network-on-chip (NoC). 479-485
  
• Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi:
  Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths. 486-503