Volume 43, Number 1, January 2010 Invited Paper
- Amir Kaivani, Ghassem Jaberipur:
Fully redundant decimal addition and subtraction using stored-unibit encoding.
- Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou:
Fast modulo 2n+1 multi-operand adders and residue generators.
- Roger Kahn, Shlomo Weiss:
Reducing leakage power with BTB access prediction.
- Rajdeep Mukhopadhyay, Anvesh Komuravelli, Pallab Dasgupta, S. K. Panda, Siddhartha Mukhopadhyay:
A static verification approach for architectural integration of mixed-signal integrated circuits.
- José M. Granado Criado, Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido:
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration.
- Bin Zhou, Yizheng Ye, Zhao-lin Li, Jianwei Zhang, Xin-chun Wu, Rui Ke:
A test set embedding approach based on twisted-ring counter with few seeds.
- Zhi Yang, Guangsheng Ma, Shu Zhang:
Formal verification of high-level data-flow synthesis designs using relational modeling and symbolic computation.
- Chiou-Yng Lee:
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m).
- Achutavarrier Prasad Vinod, Edmund Ming-Kit Lai, Douglas L. Maskell, Pramod Kumar Meher:
An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth.
- Manuel F. M. Barros, Jorge Guilherme, Nuno Horta:
Analog circuits optimization based on evolutionary computation techniques.
- Ruijing Shen, Sheldon X.-D. Tan, Ning Mi, Yici Cai:
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.
Volume 43, Number 2, April 2010 Regular papers
- Duo Li, Sheldon X.-D. Tan:
Statistical analysis of large on-chip power grid networks by variational reduction scheme.
- Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability.
- Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined intra-chip signaling for on-FPGA communications.
- Charles Thangaraj, Alkan Cengiz, Tom Chen:
Rapid design space exploration using legacy design data and technology scaling trend.
- Naifeng Jing, Weifeng He, Yongxin Zhu, Zhigang Mao:
Statistical estimation and evaluation for communication mapping in Network-on-Chip.
- Ignacio Gil, Ignasi Cairó, Javier J. Sieiro, José María López-Villegas:
Low-power current-reused RF front-end based on optimized transformers topology.
- Bassel Soudan:
Reducing signal timing variations in inter-core busses.
Volume 43, Number 3, June 2010
- Juan M. Carrillo, Guido Torelli, Raquel Pérez-Aloe, José M. Valverde, J. Francisco Duque-Carrillo:
Single-pair bulk-driven CMOS input stage: A compact low-voltage analog cell for scaled technologies.
- Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie:
Constant addition with flagged binary adder architectures.
- Ahmad Patooghy, Seyed Ghassem Miremadi, Mahdi Fazeli:
A low-overhead and reliable switch architecture for Network-on-Chips.
- A. Kabbani:
Logical effort based dynamic power estimation and optimization of static CMOS circuits.
- Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
An automated high-level topology generation procedure for continuous-time SigmaDelta modulator.
- Kai Liu, Yu Zhou, Yunsong Li, Jian Feng Ma:
A high performance MQ encoder architecture in JPEG2000.
- Yici Cai, Jin Shi, Shuai Li:
Optimization of via distribution and stacked via in multi-layered P/G networks.
Volume 43, Number 4, September 2010 Invited Paper
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- Xu He, Sheqin Dong, Yuchun Ma:
Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs.
- Jiying Xue, Tao Li, Yangdong Deng, Zhiping Yu:
Full-chip leakage analysis for 65 nm CMOS technology and beyond.
- Meysam Zargham, Christian Schlegel, Jorge Pérez Chamorro, Cyril Lahuec, Fabrice Seguin, Michel Jézéquel, Vincent C. Gaudet:
Scaling of analog LDPC decoders in sub-100 nm CMOS processes.
- Song Chen, Takeshi Yoshimura:
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints.