Journal of Circuits, Systems, and Computers, Volume 11

Volume 11, Number 1, February 2002

Giuseppe Grassi, Saverio Mascolo:
A Systematic Procedure for Synchronizing Hyperchaos Via Observer Design. 1-16
Thambipillai Srikanthan, Bimal Gisuthan:
Optimizing Scaling Factor Computations in Flat Cordic. 17-34
Hirotaka Koizumi, Iwao Sasase, Shinsaku Mori:
Analysis of Class D-E Resonant dc/dc Converter Using Thinned-Out Method. 35-50
Robert C. Chang, L.-C. Hsu, M.-C. Sun:
A Low-Power and High-Speed D Flip-Flop Using a Single Latch. 51-56
Aristodemos Pnevmatikakis, Lampros Dermentzoglou, Aggeliki Arapoyanni:
Analog-to-Digital Interface for Heterodyne Receivers. 57-72
Shaohua Tang:
Correlative Message Group Digital Signature and Its Application to E-Commerce. 73-80
Torsten Lehmann, Marco Cassia:
1 V OTA Using Current Driven Bulk Circuits. 81-92
Hong Rui Jiang, Kyung Sup Kwak:
On Modified Complex Recurrent Neural Network Adaptive Equalizer. 93-

Special Section for APCCAS 2000

Yikui Zhang, Etsuro Hayahara, Satoshi Hirano, Naohito Sakakibara:
An Optimal Design Consideration for Higher-Order Delta-Sigma AD Converter. 103-114
Yoshimasa Negishi, Eiji Watanabe, Akinori Nishihara:
An Implementation of Lattice Filters Using Four Operands Real Multiply Accumulation. 115-122
Zhengxin Hou, Wenquan Wang, Jinghui Chu:
A Kind of 2D Isotropic Wavelet and Its Application in Image Primitive Detection. 123-

Regular Papers

Ki-Seok Chung, Taewhan Kim, C. L. Liu:
A Complete Model for Glitch Analysis in Logic Circuits. 137-154
H. H. Wong, K. T. Lau:
Low Power 16 x 16 Bit Multiplier Design Using PAL-2N Logic Family. 155-164
Yi-Sheng Zhu, Wai-Kai Chen:
Short-Step Butterworth Impedance Transformers. 165-172
Hongtao Zhang, Huiyun Wang, Wai-Kai Chen:
Oversampled Chaotic Binary Sequences with Good Security. 173-186
Peter H. Bauer, Mihail L. Sichitiu, Kamal Premaratne:
Queue Control Under Time-Variant Delays: A Discrete Time System Approach. 187-

Abdhesh K. Singh, Raj Senani:
A New Four-CC-Based Configuration for Realizing a Voltage-Mode Biquad Filter. 213-218
J. Lee, Khaled Hayatleh, F. J. Lidgey, J. Drew:
Linear Bi-CMOS Transconductance for Gm-C Filter Applications. 219-230
Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, V. Adler, F. Baez, Eby G. Friedman:
Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. 231-246
Saif Zahir, Rabab K. Ward:
A New Edge Preserving Binary Images Resizing Technique. 247-258
Yoonseo Choi, Taewhan Kim:
Binding Algorithm for Power Optimization Based on Network Flow Method. 259-272
Tibor Csöndes, Balázs Kotnyek:
Greedy Algorithms for the Test Selection Problem in Protocol Conformance Testing. 273-282
Javad Haddadnia, Karim Faez, Majid Ahmadi:
A Neural Based Human Face Recognition System Using an Efficient Feature Extraction Method with Pseudo Zernike Moment. 283-304
Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Inductance Effects in RLC Trees. 305-

Ankur Srivastava, Eren Kursun, Majid Sarrafzadeh:
Predictability in RT-Level Designs. 323-332
Heng-Liang Huang, Jing-Yang Jou:
Bootstrap Monte Carlo with Adaptive Stratification for Power Estimation. 333-350
Wei-Chung Cheng, Massoud Pedram:
Power-Aware Bus Encoding Techniques for I/O and Data Buses in an Embedded System. 351-364
Yi-Jong Yeh, Sy-Yen Kuo:
An Optimization-Based Multiple-Voltage Scaling Technique for Low-Power CMOS Digital Design. 365-376
Cheng-Hsien Chen, Chen-Yi Lee:
Reduce the Memory Bandwidth of 3D Graphics Hardware with a Novel Rasterizer. 377-392
Hongchin Lin, Nai-Hsien Chen, Jainhao Lu:
Design of Modified Four-Phase CMOS Charge Pumps for Low-Voltage Flash Memories. 393-404
Jiun-In Guo, Chien-Chang Lin, Chih-Da Chien:
A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths. 405-428
Chih-Wen Lu:
Low-Power High-Speed Class-AB Buffer Amplifiers for Liquid-Crystal Display Signal Driver Application. 427-

Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram:
A Class of Irredundant Encoding Techniques for Reducing Bus Power. 445-458
Frank Vahid, Tony Givargis, Susan Cotterell:
Power Estimator Development for Embedded System Memory Tuning. 459-476
Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto:
The Impact of Source Code Transformations on Software Power and Energy Consumption. 477-502
Paul Marchal, Murali Jayapala, Samuel Xavier de Souza, Peng Yang, Francky Catthoor, Geert Deconinck:
Matador: An Exploration Environment for System-Design. 503-536
Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf:
Using Memory Compression for Energy Reduction in an Embedded Java System. 537-556
Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak:
Code Coverage-Based Power Estimation Techniques for Microprocessors. 557-

Radu Marculescu:
Guest Editorial: Power Modeling, Estimation and Optimization in VLSI Systems.
Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand:
Leakage Current in Deep-Submicron CMOS Circuits. 575-600
Seongsoo Lee, Seungjun Lee, Takayasu Sakurai:
Energy-Constrained V_DD Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems. 601-620
David Blaauw, Steven M. Martin, Trevor N. Mudge, Krisztián Flautner:
Leakage Current Reduction in VLSI Systems. 621-636
Paul-Peter Sotiriadis, Anantha Chandrakasan:
Power Estimation and Power Optimal Communication in Deep Submicron Buses: Analytical Models and Statistical Measures. 637-658
George Cai, Ashutosh S. Dhodapkar, James E. Smith:
Integrated Performance, Power, and Thermal Modeling. 659-

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