Journal of Low Power Electronics, Volume 2

Volume 2, Number 1, April 2006

• Wei-Shen Wang, Michael Liu, Michael Orshansky:
  Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation. 1-7
  

• Johan Vounckx, Vassilis Paliouras:
  Editorial.
  
• Martin Palkovic, Erik Brockmeyer, Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor:
  Systematic Preprocessing of Data Dependent Constructs for Embedded Systems. 9-1
  
• Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon:
  Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications. 18-26
  
• Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado:
  A Load-Store Queue Design Based on Predictive State Filtering. 27-36
  
• Pankaj Golani, Peter A. Beerel:
  Back-Annotation in High-Speed Asynchronous Design. 37-44
  
• David Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin:
  On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits. 45-55
  
• Ayse Kivilcim Coskun, Tajana Simunic, Kresimir Mihic, Giovanni De Micheli, Yusuf Leblebici:
  Analysis and Optimization of MPSoC Reliability. 56-69
  
• Kimish Patel, Enrico Macii, Massimo Poncino, Luca Benini:
  Energy-Efficient Value Based Selective Refresh for Embedded DRAMS. 70-79
  
• Josep Rius, Maurice Meijer, José Pineda de Gyvez:
  An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. 80-86
  
• Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero, Enrique Ostúa, Julian Viejo:
  Accurate Logic-Level Current Estimation for Digital CMOS Circuits. 87-94
  
• Philippe Manet, Renaud Ambroise, David Bol, Marc Baltus, Jean-Didier Legat:
  Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. 95-104
  
• Cristiano Forzan, Davide Pandini, Mariagrazia Graziano:
  Power Supply Selective Mapping for Accurate Timing Analysis. 105-112
  
• Radu Zlatanovici, Borivoje Nikolic:
  Power - Performance Optimization for Custom Digital Circuits. 113-120
  
• Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
  Transistor Sizing of Logic Gates to Maximize Input Delay Variability. 121-128
  

Volume 2, Number 2, August 2006

• Daniele Paolo Scarpazza, Carlo Brandolese:
  A Fast, Dynamic, Fine-Detail, Source Level Technique to Estimate the Energy Consumed by Embedded Software on Single-Issue Processor Cores. 129-139
  
• Bramha Allu, Wei Zhang:
  Reducing Instruction Translation Look-Aside Buffer Energy Through Compiler-Directed Resizing. 140-147
  
• Gayatri Mehta, Justin Stander, Joshua M. Lucas, Raymond R. Hoare, Brady Hunsaker, Alex K. Jones:
  A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. 148-164
  
• Dongkun Shin, Jihong Kim:
  Communication Power Optimization for Network-on-Chip Architectures. 165-176
  
• Yangdong Deng, Peng Li:
  Temperature-Aware Floorplanning of 3-D ICs Considering Thermally Dependent Leakage Power. 177-188
  
• Ali Mahdoum, Nadjib Badache, Hamid Bessalah:
  An Efficient Assignment of Voltages and Optional Cycles for Maximizing Rewards in Real-Time Systems with Energy Constraints. 189-200
  
• Jia Di, Jiann S. Yuan:
  Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design. 201-216
  
• Sarvesh H. Kulkarni, Dennis Sylvester:
  Power Distribution Techniques for Dual VDD Circuits. 217-229
  
• Feng Gao, John P. Hayes:
  Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction. 230-239
  
• Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula:
  Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. 240-250
  
• Tai-Hua Chen, Jinhui Chen, Lawrence T. Clark:
  Subthreshold to Above Threshold Level Shifter Design. 251-258
  
• Srikanth Mohan, Arun Ravindran, David Binkley, Arindam Mukherjee:
  Power Optimized Design of CMOS Programmable Gain Amplifiers. 259-270
  

• Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard:
  Reducing Power Dissipation in SRAM during Test. 271-280
  
• Chris J. Bleakley, Miguel Casas-Sanchez, Jose Rizo-Morente:
  Software Level Power Consumption Models and Power Saving Techniques for Embedded DSP Processors. 281-290
  
• Raimon Casanova, Ángel Dieguez, Anna Arbat, Josep Samitier:
  Multiclock Domain and Dynamic Frequency Scaling Applied to the Control Unit of a Battery Powered for 1 cm3 Microrobot. 291-299
  
• Victor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi:
  Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications. 300-307
  
• Guiomar Evans, João Goes, Nuno F. Paulino:
  Low-Voltage Low-Power Broadband CMOS Analogue Circuit for White Gaussian Noise Generation. 308-316
  
• Juan Antonio Gómez Galán, Ramón González Carvajal, Jaime Ramírez-Angulo, Antonio J. López-Martín, Carlos Rubia-Marcos:
  Super Class AB OTAs Based on Low-Power Adaptive Techniques at the Input Stage and the Active Load. 317-324
  

Volume 2, Number 3, December 2006

• Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti:
  Energy Estimation of the Memory Subsystem in Multiprocessor Systems. 325-332
  
• Kaveh Aasaraai, Amirali Baniasadi:
  Low-Power Perceptron Branch Predictor. 333-341
  
• Linwei Niu, Gang Quan:
  System Wide Dynamic Power Management for Weakly Hard Real-Time Systems. 342-355
  
• Athanasios Kakarountas, Nikolaos D. Zervas, George Theodoridis, Haralambos Michail, Dimitrios Soudris:
  Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers. 356-364
  
• Soheil Ghiasi:
  An Effective Combinatorial Algorithm for Gate-Level Threshold Voltage Assignment. 365-377
  
• Yuanlin Lu, Vishwani D. Agrawal:
  CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. 378-387
  
• Mahadevan Gomathisankaran, Akhilesh Tyagi:
  WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays. 388-400
  
• Huifang Qin, Rakesh Vattikonda, Thuan Trinh, Yu Cao, Jan M. Rabaey:
  SRAM Cell Optimization for Ultra-Low Power Standby. 401-411
  
• Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark:
  Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power. 412-424
  
• K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam:
  Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. 425-436
  
• H. Pooya Forghani-zadeh, Gabriel A. Rincón-Mora:
  Low-Power CMOS Ramp Generator Circuit for DC-DC Converters. 437-441
  
• Mohamed Ghorbel, Ahmed Ben Hamida, Mounir Samet, Jean Thomas:
  An Advanced Low Power and Versatile CMOS Current Driver for Multi-Electrode Cochlear Implant Microstimulator. 442-455
  
• Zine Abid, Hayssam El-Razouk:
  Defect Tolerant Voter Designs Based on Transistor Redundancy. 456-463
  
• V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
  On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. 464-476
  
• Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi:
  Scan-Based Structure with Reduced Static and Dynamic Power Consumption. 477-487