Journal of Low Power Electronics, Volume 3

Volume 3, Number 1, April 2007

• Wei-Shen Wang, Michael Orshansky:
  Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters. 1-12
  
• Yongkui Han, Israel Koren, C. Mani Krishna:
  TILTS: A Fast Architectural-Level Transient Thermal Simulation Method. 13-21
  
• Yang Xu, Hu He, Zhou Zhixiong, Yanjun Zhang, Yihe Sun:
  Heuristic on a Novel Power Management System Cooperating with Compiler. 22-27
  
• Anand Ramalingam, Anirudh Devgan, David Z. Pan:
  Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. 28-35
  
• Giuseppe Notarangelo, Francesco Pappalardo, Elena Salurso, Elio Guidetti:
  A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing. 36-42
  
• Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai:
  Exploiting Speculation Cost Prediction in Power-Aware Applications. 43-53
  
• Joachim Fenkes, Tobias Gemmeke, Jens Leenstra:
  Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process. 54-59
  
• Steven D. Tucker, Arun Ravindran, Christopher Wichman, Arindam Mukherjee:
  Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters. 60-69
  
• David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
  Improving the Performance of Static CMOS Gates by Using Independent Bodies. 70-77
  
• Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee:
  Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption. 78-95
  
• Domenico Zito, Domenico Pepe, Bruno Neri:
  RFID Systems: Passive versus Active and a Novel Low-Power RF Transceiver for IEEE 802.15.4 (ZigBee) Standard Based Applications. 96-105
  
• Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy:
  Low-Power Hierarchical Scan Test for Multiple Clock Domains. 106-118
  

Volume 3, Number 2, August 2007

• Nagm Eldin Mohamed, Adil Akaaboune, Nazeih Botros:
  Lethargic Cache: A Low Leakage Direct Mapped Cache. 119-123
  
• Woongki Baek, Young-Jin Kim, Jinhyo Kim, Jihong Kim:
  A Measurement-Based Automatic Energy Optimization Technique for Embedded Applications. 124-132
  
• Giuseppe Visalli, Elio Guidetti:
  An Ultra-Low Power Data Aggregation System for Wireless Micro Sensor Networks. 133-140
  
• Yongkui Han, Israel Koren:
  Simulated Annealing Based Temperature Aware Floorplanning. 141-155
  
• Gaurav Singh, Jacob B. Schwartz, Sumit Ahuja, Sandeep K. Shukla:
  Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications. 156-166
  
• Brajesh Pandey, Arun N. Chandorkar:
  Precision Low Voltage and Current References. 167-174
  
• Walid Elgharbawy, Pradeep Golconda, Abdelhamid G. Moursy, Magdy A. Bayoumi:
  Novel Adaptive Body Biasing Techniques for Energy Efficient Subthreshold CMOS Circuits. 175-188
  
• Alberto García Ortiz, Tudor Murgan, Manfred Glesner:
  Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear Systems. 189-198
  
• Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri:
  DFT MAX and Power. 199-205
  
• Chun-Yi Lee, James Chien-Mo Li:
  Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing. 206-216
  
• Craig A. Dolwin, Hatem Yassine:
  Evaluation of an Adaptive Dynamic Voltage Scaling Scheme for Hard Real-Time Applications. 217-221
  

Volume 3, Number 3, December 2007

• Louis P. Alarcón, Tsung-Te Liu, Matthew D. Pierson, Jan M. Rabaey:
  Exploring Very Low-Energy Logic: A Case Study. 223-233
  
• Peter A. Beerel, Marly Roncken:
  Low Power and Energy Efficient Asynchronous Design. 234-253
  
• Nilanjan Banerjee, Kaushik Roy:
  Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing. 254-270
  
• Yaseer A. Durrani, Teresa Riesgo:
  Architectural Power Analysis for Intellectual Property-Based Digital System. 271-279
  
• K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula:
  Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits. 280-292
  
• Dhireesha Kudithipudi, Eugene John:
  Static Power Analysis and Estimation in Ternary Content Addressable Memory Cells. 293-301
  
• Young-Jin Kim, Jihong Kim:
  Energy-Efficient Techniques for Disk-Based Mobile Systems. 302-317
  
• Haifeng Qian, Emrah Acar:
  Timing-Aware Power Minimization via Extended Timing Graph Methods. 318-326
  
• George N. Selimis, Athanasios P. Kakarountas, Apostolos P. Fournaris, Athanasios Milidonis, Odysseas G. Koufopavlou:
  A Low Power Design for Sbox Cryptographic Primitive of Advanced Encryption Standard for Mobile End-Users. 327-336
  
• Rajeevan Chandel, Sankar Sarkar, Ashwani Kumar Chandel:
  Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects. 337-344
  
• Armin Tajalli, Paul Muller, Yusuf Leblebici:
  Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits. 345-354
  

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