Journal of Low Power Electronics, Volume 7
Volume 7, Number 1, February 2011
Shireesh Verma: A Special Issue on Low Power Design and Verification Techniques. 1- Daniel Calvo, Pablo González, Luis Diaz, Hector Posadas, Pablo Sánchez, Eugenio Villar, Andrea Acquaviva, Enrico Macii: A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design. 2-16
- Weixun Wang, Prabhat Mishra: Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems. 17-28
- Dmitrij Kissler, Frank Hannig, Jürgen Teich: Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. 29-40
- Malal Bathily, Bruno Allard, Frederic Hasbani, Vincent Pinon: Low-Power, Battery-Operated, Large-Bandwidth Analog Integrated DC/DC Step-Down Converters. 49-60
- He Tang, Hui Zhao, Siqiang Fan, Xin Wang, Lin Lin, Qiang Fang, Jian Liu, Albert Z. Wang: Design Matrix Analysis for Capacitive Interpolation Flash ADC. 61-70
- Yi Zhang, Rajdeep Bondade, Dongsheng Ma: On-Chip Single-Inductor Multiple-Output Power Converter Design with Adaptive Cross Regulation and Supply Variation Control for Power-Efficient VLSI Systems. 71-86
- Ji-Hye Bong, Kwan-Hee Jo, Kyeong-Sik Min, Sung-Mo Kang: Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits. 87-95
- Abhijit Sil, Magdy Bayoumi: A Bit-Interleaved 2-Port Subthreshold 6T SRAM Array with High Write-Ability and SNM-Free Read in 90 nm. 96-109
- Hanhua Qian, Xiwei Huang, Hao Yu, Chip-Hong Chang: Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling. 110-121
Volume 7, Number 2, April 2011
- Edoardo Regini, Daeseob Lim, Tajana Simunic Rosing: Resource Management in Heterogeneous Wireless Sensor Networks. 123-140
- Sohaib Majzoub: Instruction-Based Voltage Scaling for Power Reduction in SIMD MPSoCs. 141-147
- Jeff Pool, Anselmo Lastra, Montek Singh: Power-Gated Arithmetic Circuits for Energy-Precision Tradeoffs in Mobile Graphics Processing Units. 148-162
- Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, Ashok K. Saxena, Sudeb Dasgupta: Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology. 163-171
- J. Kevin Hicks, Dhireesha Kudithipudi: Hybrid Subthreshold and Nearthreshold Design Methodology for Energy Minimization. 172-184
- Judit Freijedo, María Dolores Valdés, Lucía Costas, María José Moure, Juan J. Rodríguez-Andina, Jorge Semião, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira: Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing. 185-198
- Aya Mabrouki, Thierry Taris, Yann Deval, Jean-Baptiste Begueret: An Optimum Body Biasing for Gain and Linearity Control in CMOS Low-Noise Amplifiers. 199-208
- Svetozar S. Broussev, Nikolay T. Tchamov: Evaluation of Parasitic Components in LC Oscillators by Time-Varying Root-Locus. 209-217
- Bruno Jacinto, Carlos Moreira, Marcelino Santos: Digital Sliding Mode Control of DC-DC Buck Converters. 218-233
- Miao Hu, Hai Helen Li, Yiran Chen, Xiaobin Wang: Spintronic Memristor: Compact Model and Statistical Analysis. 234-244
- Irith Pomeranz, Sudhakar M. Reddy: Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan. 245-253
- René van Leuken: Selected Articles from the PATMOS 2010 Workshop. 254
- Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiss, Josef Haid: An Automated Power Emulation Framework for Embedded Software - Detecting Power-Critical Code Regions and Optimizing Software-Induced Power Consumption Peaks. 255-264
- Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh: On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling. 265-273
- Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev: Self-Timed SRAM for Energy Harvesting Systems. 274-284
- Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici: Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing. 285-293
- Cristiano Lazzari, Jorge Fernandes, Paulo F. Flores, José Monteiro: Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. 294-301
Volume 7, Number 3, August 2011
- Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty: Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework. 303-313
- Md. Ibrahim Faisal, Zahra Jeddi, Esmaeil Amini, Magdy Bayoumi: A Flexible Architecture for Finite Field Galois Fields(2m) Arithmetic Processor. 314-327
- Carolina Albea, Diego Puschini, Pascal Vivet, Ivan Miro Panades, Edith Beigné, Suzanne Lesecq: Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures. 328-340
- Rashmi Nanda, Dejan Markovic: Energy-Efficient Retiming and Scheduling of Datapath-Dominant Digital Systems. 341-349
- Satendra Kumar Maurya, Lawrence T. Clark: A Specialized Static Content Addressable Memory for Longest Prefix Matching in Internet Protocol Routing. 350-363
- Rashmi Mehrotra, Tom English, Michel P. Schellekens, Steve Hollands, Emanuel M. Popovici: Timing-Driven Power Optimisation and Power-Driven Timing Optimisation of Combinational Circuits. 364-380
- Jitendra Kanungo, S. Dasgupta: An Efficient Single Phase Adiabatic Logic and Its Application to Combinational and Sequential Design. 381-392
- Yangbo Wu, Jianping Hu: Near-Threshold Computing of Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Circuits. 393-402
- Basab Datta, Wayne Burleson: Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies. 403-419
- Biswajit Patra, Nayan Chandak, Amlan Chakrabarti: An Efficient Methodology for Full Chip Signal ElectroMigration Analysis for Advanced Technology Node Designs. 420-425
- José F. da Rocha, Marcelino Bicho Dos Santos, José M. Dores Costa: Smart Control of Internal Supply Voltage Spikes in a Low Voltage DC-DC Buck Converter. 426-443
- David Guerrero, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo: Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. 444-452
- Benjamin S. Mericli, Ajay Ogirala, Peter J. Hawrylak, Marlin H. Mickle: A Passive Radio Frequency Amplifier for Radio Frequency Identification Tags. 453-458
Volume 7, Number 4, December 2011
- Nitin Chandrachoodan, Shankar Balachandran: 24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011. 459
- Kyungseok Kim, Vishwani D. Agrawal: Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply. 460-470
- Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski: A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. 471-481
- Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien: A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters. 482-489
- Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac: Trading Accuracy for Power in a Multiplier Architecture. 490-501
- Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi: Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test. 502-515
- Tapas Kumar Kundu, Kolin Paul: Analyzing and Improving Performance and Energy Efficiency of Android. 516-528
- Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt, Leticia Maria Veiras Bolzani Poehls, Fabian Vargas, Yervant Zorian: 12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. 529-530
- András Timár, Márta Rencz: Studying the Influence of Chip Temperatures on Timing Integrity Using Improved Power Modeling. 531-540
- Laurent Bousquet, Fabio Cenni, Emmanuel Simeu: Inclusion of Power Consumption Information in High-Level Modeling of Linear Analog Blocks. 541-551
- Claas Cornelius, Frank Sill Torres, Dirk Timmermann: Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits. 552-561
- R. S. Oliveira, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira: On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications. 562-572
- Sobeeh Almukhaizim, Eman AlQuraishi, Ozgur Sinanoglu: Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits. 573-584
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last updated on 2013-06-19T203413 by the dblp team