Microprocessing and Microprogramming, Volume 35

Volume 35, Numbers 1-5, September 1992

• Francis Jutand:
  Chairman's introduction. vii
  
• Benny Graff Mortensen:
  Program chairman's introduction. ix
  
• Yale N. Patt:
  Highest performance computing machines. 1
  
• Nicolas Demassieux:
  From image coding to multimedia: Algorithms and architectures for a revolution. 3
  
• Harold W. Lawson:
  Application machines: An approach to realizing understandable systems. 5-10
  
• Petri Pulli, René Elmstrøm:
  IPTES - Incremental Prototyping Technology for Embedded real-time Systems. 13-21
  
• Eike Best:
  Results of the esprit basic research action 3148 demon (design methods based on nets). 23-27
  
• Kees M. van Hee, Theodor Hildebrand, Sergio Copelli:
  PROOFS: Application engineering based on formal methods. 29-36
  
• Rumen Stainov, Winfried Kalfa:
  A light weight kernel server. 39-45
  
• Luc Courtrai, Jean-François Roos, Jean-Marc Geib, Jean-François Méhaut:
  Communicating active components: An environment for concurrent applications on parallel machines. 47-54
  
• Izidor Jerebic:
  TriOS operating system. 55-60
  
• Georg Klein-Heßling:
  Specification and design of concurrent control units. 63-70
  
• K. C. Huang, T. S. Nain, W. S. Hsieh, C. S. Yang, C. S. Lu:
  EPVD: An interactive protocol specification and validation environment in Estelle formal specification. 71-77
  
• Klaus Hoffmann:
  An interactive environment for the model-based design of analog circuits. 79-85
  
• Chien-Chao Tseng, Chih-Zong Lin, Jiunn-Kai Hwang, Kuo-Tai Lin:
  A data driven hybrid computer architecture. 89-96
  
• Giovanni Dimauro, Sebastiano Impedovo, Giuseppe Pirlo:
  A new magnitude function for fast numbers comparison in the residue number system. 97-104
  
• Franck Cappello, Jean-Luc Béchennec, J.-L. Glavitto:
  Design of the processing node of the PTAH 64 parallel computer. 105-111
  
• Michel Dauphin:
  SPECS: Formal methods and techniques for telecommunications software development. 117-124
  
• B. Boittiaux, G. Goncalves, M. P. Haye:
  A transputer network for a device simulator. 127-132
  
• Jean Paul Calvez, Olivier Pasquier:
  Implementation of statecharts with transputers. 133-139
  
• A. Sinha, P. K. Das, A. Chaudhuri:
  Checkpointing and recovery in a pipeline of transputers. 141-147
  
• A. J. W. M. ten Berg:
  Estimators for logic minimization and implementation selection of finite state machines. 151-158
  
• Lech Józwiak, Hein Mijland:
  On the use of OR-BDDs for test generation. 159-166
  
• Jacek Gawin:
  Modelling of digital circuits function and functional faults on register transfer level. 167-172
  
• Cesare Alippi, Marley B. R. Vellasco:
  Galatea neural VLSI architectures: Communication and control considerations. 175-180
  
• Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto, Renato Stefanelli:
  A behavioral approach to testability analysis for neural networks. 181-186
  
• Veselko Gustin:
  Artificial neural network realization with programmable logic circuit. 187-192
  
• Massimo Ancona, P. Nieddu:
  A trip to object-oriented land. 195-202
  
• Wolfgang Pree, Gustav Pomberger:
  Object-oriented versus conventional software development: A comparative case study. 203-211
  
• Antonio Camurri, Paolo Franchi, Maurizio Vitale:
  An object-oriented approach to High-Level Petri Nets. 213-220
  
• Harald Schaschinger:
  Object-oriented analysis and modeling with the ESAstation. 221-227
  
• Edwige E. Pissaloux, D. H. Schaefer, Samir Bouaziz, Francis Devos:
  MPPNL - A Petri Net based Language to design fine-grained parallel machines and debug their software. 231-236
  
• Rina Das, D. Q. M. Fay, Pradip K. Das:
  Allocation of precedence-constrained tasks to parallel processors for optimal execution. 237-244
  
• Erik Maehle, Wolfgang Obelöer:
  DELTA-T: A user-transparent software-monitoring tool for multi-transputer systems. 245-252
  
• S. Arunkumar, R. Lal, R. Venkatagopal:
  SIMPAC-T : A simulator for multitransputer systems. 253-260
  
• Adam Pawlak:
  High-level synthesis. 261
  
• Zebo Peng:
  Digital system simulation with VHDL in a high-level synthesis system. 263-269
  
• François Verdier, Abdelhakim Safir, Bertrand Zavidovique:
  A high level synthesis algorithm including control constraints. 271-278
  
• P. Bakowski, Jean Paul Calvez:
  System performance modeling with functional schemes and VHDL. 279-285
  
• N. Hendrich, J. Lohse, Reinhard Rauscher:
  Silicon compilation and rapid prototyping of microprogrammed VLSI-Circuits with MIMOLA and SOLO 1400. 287-294
  
• Thomas Kolarz:
  Performance evaluation: An analytical model for calculating start misses in caches. 297-302
  
• H. Barsuhn, W. Lochlein, D. Wendel, U. Wille, P. Coppens:
  Level-2 cache for high performance /390 μ-processors. 303-309
  
• Douglas Renaux, Paul P. Dasiewicz:
  A clause indexing unit for prolog. 311-318
  
• Eberhard Zehendner:
  Efficient implementation of regular parallel adders for binary signed digit number representations. 319-326
  
• Yongun Yoon, Key-Sun Choi, Gil-Chang Kim, Dongwook Shin:
  A hybrid knowledge-based approach to information retrieval. 329-336
  
• Joon Ho Lee, Myoung-Ho Kim, Yoon-Joon Lee:
  Enhancing the fuzzy set model for high quality document rankings. 337-344
  
• Jae-Woo Chang, Jae Soo Yoo, Yoon-Joon Lee:
  Performance comparison of signature-based multikey access methods. 345-352
  
• L. P. M. Benders, M. P. J. Stevens:
  Task level specification and communication. 355-362
  
• Andrew M. Tyrrell, Geof F. Carpenter:
  The specification and design of atomic actions for fault tolerant concurrent software. 363-368
  
• Monika Kapus-Kolar:
  Deriving protocol specifications from service specifications including multirendezvous. 369-374
  
• Uwe Hübner, Wolfgang Meyer, Heinrich Theodor Vierhaus:
  CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents. 377-382
  
• M. Saraiva, Marcelino B. Santos, Antonio Casimiro, Isabel Maria Cacho Teixeira, João Paulo Teixeira:
  On the design of a highly testable cell library. 383-389
  
• Giacomo Buonanno, Micaela Serra:
  State assignment and testability of PLA-based finite state machines. 391-398
  
• David R. Kaeli, Philip G. Emma, Joshua W. Knight, Thomas R. Puzak:
  Contrasting instruction-fetch time and instruction-decode time branch prediction mechanisms: Achieving synergy through their cooperative operation. 401-408
  
• Theodore Antonakopoulos, J. Koutsonikos, Vassilios Makios:
  An adaptable frame multiplexing scheme for source routing bridges. 409-416
  
• Francesco Gregoretti, Leonardo Maria Reyneri, Claudio Sansoè, L. Rigazio:
  A chip set implementation of a parallel cellular architecture. 417-425
  
• Sukhoon Kang, Songchun Moon:
  An integrated access control in heterogeneous distributed database systems. 429-436
  
• Buhyun Hwang, Songchun Moon:
  Transaction management for global serializability and local autonomy in multidatabase systems. 437-444
  
• Heonguil Lee, Jungwan Cho, Jinho Kim:
  Development of a real-time database management system for production process-control applications. 445-452
  
• John G. Vaughan:
  The dining philosophers problem and its decentralisation. 455-462
  
• Gianluigi Alari, Augusto Ciuffoletti:
  Improving the probabilistic clock synchronization algorithm. 463-467
  
• Franck Delaplace, Franck Cappello:
  Data layouts impacts on the compilation of the communications for a synchronous MSIMD machine. 469-475
  
• H. A. Farhat, S. G. From, Antonio Lioy:
  A quadratic programming approach to estimating the testability and coverage distributions of a VLSI circuit. 479-483
  
• Xinli Gu, Krzysztof Kuchcinski, Zebo Peng:
  An approach to testability analysis and improvement for VLSI systems. 485-492
  
• Mark Royals, Tassos Markas, Nick Kanopoulos:
  A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port. 493-500
  
• Antti Laine, Juha Viskari:
  UISER - a customizable software engineering environment for development-in-the-large. 505-512
  
• Jesús Sánchez Allende, Gonzalo León Serrano:
  PTD: Architectural system description support based on visual specification languages. 513-520
  
• Michael Andersen, René Elmstrøm, Poul Bøgh Lassen, Peter Gorm Larsen:
  Making specifications executable - Using IPTES Meta-IV. 521-528
  
• Olivier Pasquier, Jean Paul Calvez:
  A software generator for multi-transputer-based real-time applications. 529-536
  
• Edwige E. Pissaloux:
  Session F2: Parallel architectures I. 537-538
  
• Roman Wyrzykowski, Juri Kanevski, Sergej Ovramenko:
  Dependence graph transformations in the design of processor arrays for matrix multiplications. 539-544
  
• Hong Shen, Ralph-Johan Back:
  Construction of large-size interconnection networks with high performance. 545-554
  
• Alexandre Malheiros Meslin, Ageu Cavalcanti Pacheco Jr., Júlio S. Aude:
  A comparative analysis of cache memory architectures for the MULTIPLUS multiprocessor. 555-562
  
• Rafael D. Lius:
  A multi-processor shared memory architecture for parallel cyclic reference counting. 563-568
  
• R. Michl, B. Riedlinger, F. J. Schmitt:
  Constructive evaluation of computer architectures: A CAD approach. 571-578
  
• Panayotis Tsanakas, George K. Papakonstantinou, Nikolaos Bilalis:
  Systematic synthesis of parallel VLSI architectures from FP specifications and its application to scene matching. 579-586
  
• Jürgen Herrmann, Renate Beckmann:
  LEFT - A learning tool for early floorplanning. 587-594
  
• C. Carrière, Michel Auguin, Fernand Boéri, G. Menez:
  A comparison study of minimization methods of unit interconnection in VLIW processors. 595-602
  
• Steen Silberg:
  Intel i860 versus Digital Signal Processors (DSP). 605-610
  
• Helmut Steckenbiller, Herbert Plansky:
  A low cost solution for HDTV data reduction. 611-618
  
• Andrew M. Tyrrell, David M. Howard, Nicola A. Beasley:
  Transputer model of the human peripheral hearing system. 619-624
  
• Antonio Camurri, Carlo Innocenti, Claudio Massucco, Renato Zaccaria:
  A software architecture for sound and music processing. 625-632
  
• Hans Berggren, Mikael Gustafsson, Lennart Lindh:
  Measuring and analyzing real-time kernel performance. 635-640
  
• Tatjana Kapus, Bogomir Horvat:
  Verifying networks of processes that communicate via shared variables. 641-649
  
• Imrich Chlamtac, K. G. Satam:
  ETS - a performance prediction tool for protocols specified in FDT Estelle. 651-658
  
• Tsung-Chuan Huang, Chu-Sing Yang, K. C. Huang:
  Fault diagnosis for the generalized Boolean n-cube network. 661-665
  
• Chu-Sing Yang, Y. M. Tsai, R. L. Wu:
  Fault tolerant wormhole routing in hypercube multicomputers. 667-672
  
• Chu-Sing Yang, S. Y. Wu, Wen-Shyong Hsieh, K. C. Huang:
  A reconfigurable boolean n-cube architecture under faults. 673-679
  
• Elmar U. K. Melcher, Wolfgang Röthig, Michel Dana:
  Multiple input transitions in CMOS gates. 683-690
  
• Wolfgang Röthig, Elmar U. K. Melcher, Sami Chakroun, Michel Dana:
  Power consumption estimation using statistical signal properties. 691-696
  
• Helmut E. Graeb, Reiner E. Lederle:
  Circuit yield optimization by analyzing performance statistics. 697-703
  
• R. Welter, Georg Thiele, D. Popovic, E. Wendland:
  A pearl-based multi-loop and multi-sequence controller. 707-712
  
• Nixon C. M. Leung, C. K. Li, P. K. Kung:
  Design of a DSP-based discrete variable structure controller with improved robustness. 713-717
  
• Ann Nowé:
  A self-tuning robust fuzzy controller. 719-726
  
• Ludo Cuypers:
  Automated implementations of Lotos specification. 729-735
  
• L. Carcagno, Marianne De Michiel, Daniel Dours, Roland Facca, A. Feki, Patrick Magnaud:
  From specification to implementation of a real-time system. 737-744
  
• Magali E. Azema-Barac, Apostolos Nikolaos Refenes:
  Neural network implementations and speed-up on Massively Parallel machines. 747-754
  
• Ioannis P. Vlahavas, Petros Kefalas:
  An abstract prolog machine based on parallel resolution principle. 755-762
  
• Jan van Oorschot, Anton Dekkers:
  Measuring and simulating an 802.3 CSMA/CD LAN. 765-772
  
• Michael E. Woodward:
  Stochastic modelling of a high speed, short packet length, slotted ring with finite queueing capacity. 773-779
  
• Apostolos Nikolaos Refenes, E. B. Chan:
  Sound recognition and optimal neural network design. 783-789
  
• Yung-Nien Sun, Ching-Tsorng Tsai:
  Segmentation of echocardiograms using a neural network. 791-798
  

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