Journal of Systems Architecture, Volume 42

Volume 42, Number 1, 1996

• Gil-Haeng Lee, Heung-Kyu Lee, Jung-Wan Cho:
  A prediction-based adaptive location policy for distributed load balancing. 1-18
  
• Timo Hämäläinen, Harri Klapuri, Jukka Saarinen, Pekka Ojala, Kimmo Kaski:
  Accelerating genetic algorithm computation in tree shaped parallel computer. 19-36
  
• Chan-Ik Park, Kyung Sook Hwang:
  Performance analysis of hybrid disk array architectures to meet I/O requirements. 37-53
  
• Stergios Papadimitriou, Anastasios Bezerianos:
  Multiresolution analysis and denoising of computer performance evaluation data with the wavelet transform. 55-65
  
• Nabanita Das, Jayasree Dattagupta:
  Fault identification and routing in Benes networks. 67-81
  
• W. Lin, Eric W. S. Chen:
  Looping adjacent nodes on multistage interconnection networks. 83-93
  

Volume 42, Number 2, September 1996

• Donatella Sciuto:
  VHDL( VHSIC Hardware Description Language). 95-96
  
• Lennart Lindh, Johan Stärner, Joakim Adomat:
  Experiences with VHDL and FPGAs. 97-104
  
• Manfred Selz, Wolfgang Ecker, Eugenio Villar:
  VHDL synthesis description portability: The need for Level synthesis subsets. 105-116
  
• Wolfgang Ecker:
  Verification methods for VHDL RTL-subroutines. 117-128
  
• Marco Avvenuti, Luigi Rizzo, Lorenzo Vicisano:
  Hardware support for load sharing in parallel systems. 129-143
  
• Byungwook Kim, Songchun Moon:
  A new indexing scheme supporting multi-attribute database applications: MAX. 144-162
  

Volume 42, Number 3, October 1996

• Jaafar Gaber, Bernard Toursel, Gilles Goncalves, Tinte Hsu:
  Embedding trees in massively parallel computers. 165-170
  
• Zuqiang Fu, Eric M. Dowling, Ronald D. DeGroat:
  Systolic MIMD architectures for 4-level spherical subspace tracking. 171-193
  
• Ji-Yun Kim, Hyunsoo Yoon, Seung Ryoul Maeng, Jung Wan Cho:
  Drop-and-reroute: A new flow control policy for adaptive wormhole routing. 195-209
  
• Hu-Jun Wang, Jian Li:
  Bandwidth of prioritized crossbar systems. 211-223
  
• G. M. Chaudhry, A. N. Khan:
  Bandwidth of a reconfigurable multiple-group multiprocessor system. 225-234
  
• Antti Auer, Jukka Karjalainen, Veikko Seppänen:
  Improving R & D processes by an ISO 9001-based quality management system. 235-244
  

Volume 42, Number 4, November 1996

• Heping He, Hussein Zedan:
  A fast prototype tool for parallel reactive systems. 251-266
  
• Alessandro Genco, Giuseppe Lo Re:
  The egoistic approach to parallel process migration into heterogeneous workstation network. 267-278
  
• Nidhi Agrawal, C. P. Ravikumar:
  Fault-tolerant routing in multiply twisted cube topology. 279-288
  
• Wei-Kuo Chiang, Rong-Jaye Chen:
  Topological properties of hierarchical cubic networks. 289-307
  
• Prabir Bhattacharya:
  Connected component labeling for binary images on a reconfigurable mesh architecture. 309-313
  
• Pranay Chaudhuri:
  Parallel updating algorithms for graph searching problems. 315-325
  

Volume 42, Number 5, November 1996

• Skillicorn B. Skillicorn:
  Towards a framework for cost-based transformation. 331-340
  
• Claudia Di Napoli, Maurizio Giordano, Mario Mango Furnari, Renata Napolitano:
  A portable parallel environment for complex systems simulation through cellular automata networks. 341-350
  
• Joao Paulo Kitajima, Brigitte Plateau, Pascal Bouvry, Denis Trystram:
  ANDES: Evaluating mapping strategies with synthetic programs. 351-365
  
• Jie Wu:
  Optimal broadcasting in hypercubes with link faults using limited global information. 367-380
  

Volume 42, Numbers 6-7, December 1996

• Lorenzo Mezzalira:
  Real-time systems. 387-390
  
• Ana García-Fornes, Houcine Hassan, Alfons Crespo:
  Strategies for scheduling optional tasks in intelligent real-time environments. 391-407
  
• Ramesh Yerraballi, Ravi Mukkamala:
  Scalability in real-time systems with end-to-end requirements. 409-429
  
• José Javier Gutiérrez García, Michael González Harbour:
  Minimizing the effects of jitter in distributed hard real-time systems. 431-447
  
• Jakob Axelsson:
  Hardware/software partitioning aiming at fulfilment of real-time constraints. 449-464
  
• Moreno Coli, Paolo Palazzari:
  Real time pipelined system design through simulated annealing. 465-475
  
• Flavio De Paoli, Francesco Tisato, Carlo Bellettini:
  HyperReal: A modular control architecture for HRT systems. 477-487
  
• Jozef Hooman, Jüri Vain:
  Integrating methods for the design of real-time systems. 489-502
  
• Oliver Botti, Lorenzo Capra:
  A GSPN based methodology for the evaluation of concurrent applications in distributed plant automation systems. 503-530
  
• Victor C. S. Lee, Kam-yiu Lam, Sheung-lun Hung:
  Impact of high speed network on performance of real-time concurrency control protocol. 531-546
  
• Young-Kuk Kim, Matthew R. Lehr, Sang H. Sona:
  Software architecture for a firm real-time database system. 547-562
  
• Ye-In Chang:
  A hybrid distributed mutual exclusion algorithm. 563-564
  

Volume 42, Number 8, December 1996

• Gerhard Chroust:
  ESPITI. 571-572
  
• Ingward Bey:
  ESPITI - a european challenge. 573-577
  
• Kevin Eakin:
  Implementing ESPITI on a European scale. 579-582
  
• Milagros Ibáñez, Hans-Jürgen Kugler, Santiago Rementeria:
  Has Europe learnt enough? 583-590
  
• Gerhard Chroust:
  What is a software process? 591-600
  
• Klaus Plögert:
  The tailoring process in the German V-Model. 601-609
  
• Adriana Bicego, Pasi Kuvaja:
  Software process maturity and certification. 611-620
  
• Volkmar H. Haase:
  Software process assessment concepts. 621-631
  
• Jean-Martin Simon:
  SPICE: Overview for software process improvement. 633-641
  
• Antti Auer, Jukka Karjalainen, Veikko Seppänen:
  Improving R&D processes by an ISO 9001-based Quality Management System. 643-651
  
• Erwin Schoitsch:
  Software processes, assessment and ISO 9000-certification: A user's view. 653-661
  

Volume 42, Numbers 9-10, February 1997

• Krzysztof Kuchcinski:
  Design of hardware and software systems. 663-664
  
• D. Bryan Perdue, Daniel Tabak:
  Interconnection network analysis for a compliant massively parallel processor. 665-678
  
• Marco Avvenuti, Luigi Rizzo, Lorenzo Vicisano:
  A hybrid approach to adaptive load sharing and its performance. 679-696
  
• M. D. Edwards, J. Forrest, A. E. Whelan:
  Acceleration of software algorithms using hardware/software co-design techniques. 697-707
  
• Domingo Benítez-Díaz:
  Modular architecture for custom-built systems oriented to real-time computer vision: Application to color recognition. 709-723
  
• Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli:
  Post-synthesis back-annotation of timing information in behavioral VHDL. 725-741
  
• Stavros D. Nikolopoulos, George Samaras:
  Sub-optimal solutions to track detection problem using graph theoretic concepts. 743-760
  
• Kuo-Liang Chung:
  Embedding a complete binary tree into the supercube. 761-763
  

Last update Fri May 24 20:37:08 2013 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page