Journal of Systems Architecture, Volume 44

Volume 44, Number 1, October 1997

• Donatella Sciuto:
  Special section on VHDL. 1-2
  
• Cristiana Bolchini, Luciano Baresi:
  Software methodologies in VHDL code analysis. 3-21
  
• Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee:
  Implications of VHDL timing models on simulation and software synthesis. 23-36
  
• William Fornaciari, Paolo Gubian, Donatella Sciuto, Cristina Silvano:
  A VHDL-based approach for power estimation of embedded systems. 37-61
  
• Gustavo I. E. Cancelo, Sten Hansen:
  NETMAP: An integrated system for building analog neural networks. 63-73
  

Volume 44, Number 2, November 1997

• Ammar Attoui:
  An environment based on rewriting logic for parallel systems formal specification and prototyping. 79-105
  
• Alan Burns, Andy J. Wellings:
  Synchronous sessions and fixed priority scheduling. 107-118
  
• Seok-Hee Hong, Myoung-Ho Kim:
  A real-time concurrency control algorithm: Use of multiversion and precedence relationships. 119-130
  
• Kiyoung Kim, Songchun Moon:
  Dynamic multi-granularity locking for coordinating cooperative activities. 131-142
  
• Ranjani Parthasarathi, Ashok Jhunjhunwala:
  Multiple precision square root using the Dwandwa square-root algorithm. 143-158
  

Volume 44, Numbers 3-4, 1998

• Djamshid Tavangarian:
  Special issue on cluster computing. 163-168
  
• Andreas Polze, Miroslaw Malek:
  Network computing with SONiC. 169-187
  
• Xingfu Wu, Wei Li:
  Performance models for scalable cluster computing. 189-205
  
• Gunther Hipper, Djamshid Tavangarian:
  Advanced workstation cluster architectures for parallel computing. 207-226
  
• Hans Eberle:
  Switcherland: A scalable interconnection structure for distributed systems. 227-240
  
• Thomas M. Warschko, Joachim M. Blum, Walter F. Tichy:
  ParaStation: Efficient parallel computing by clustering workstations: Design and evaluation. 241-260
  
• Alexander Reinefeld, Jörn Gehring, Matthias Brune:
  Communicating across parallel message-passing environments. 261-272
  
• Kam Hong Shum:
  Replicating parallel simulation on heterogeneous clusters. 273-292
  
• Bernd Dreier, Annja Huber, Theo Ungerer, Markus Zahn:
  Trading computing power with ReGTime. 293-306
  

Volume 44, Number 5, February 1998

• Kyeonghoon Koo, Gab Seon Rho, Wook Hyun Kwon, Jaehyun Park, Naehyuck Chang:
  Architectural design of an RISC processor for programmable logic controllers. 311-325
  
• K. Arun, N. Vivekananda, D. Janaki Ram:
  A concurrency control model for real-time distributed collaboration. 327-341
  
• Maximilian Frey, Marjeta Pucko:
  Formal specification of CSCW applications with concurrent abstract data types. 343-357
  
• M. P. Sebastian, P. S. Nagendra Rao, Lawrence Jenkins:
  Properties and performance of folded cube-connected cycles. 359-374
  
• Kuo-Liang Chung:
  Log-time delay consideration on mesh with multiple buses. 375-382
  
• Ivan Z. Milentijevic, Igor Z. Milovanovic, Emina I. Milovanovic, Milorad B. Tosic, Mile K. Stojcev:
  Two-level pipelined systolic arrays for matrix-vector multiplication. 383-387
  

Volume 44, Numbers 6-7, March 1998

• Simon J. E. Taylor:
  Parallel and distributed simulation. 393-394
  
• Stephen John Turner:
  Models of computation for parallel discrete event simulation. 395-409
  
• Wouter Brissinck, Erik F. Dirkx:
  Analysis of large ATM switches using a platform-independent simulation environment. 411-431
  
• Hyung Kim Ki, Tag Gon Kim, Kyu Ho Park:
  Hierarchical partitioning algorithm for optimistic distributed simulation of DEVS models. 433-455
  
• Karim Djemame, Dennis C. Gilles, Lewis M. Mackenzie, Mohamed Bettaz:
  Performance comparison of high-level algebraic nets distributed simulation protocols. 457-472
  
• Kothanda Umamageswaran, Krishnan Subramani, Philip A. Wilsey, Perry Alexander:
  Formal verification and empirical analysis of rollback relaxation. 473-495
  
• Stefan Schöf:
  Efficient data structures for Time Warp simulation queues. 497-517
  
• José Miguel-Alonso, Agustin Arruabarrena, Ramón Beivide, José A. B. Fortes:
  An evaluation of implementations of the CMB parallel simulation algorithm on distributed memory multicomputers. 519-545
  
• Nasser Kalantery:
  A distributed event processing method for general purpose computation. 547-558
  

Volume 44, Number 8, April 1998

• Vincenzo Piuri, Cesare Alippi:
  Artificial neural networks. 565-567
  
• Igor Ratner, Hassan Ali, Emil M. Petriu:
  Neural network simulation of a dielectric ring resonator antenna. 569-581
  
• Javier Fernández de Cañete, Alfonso García-Cerezo, Inmaculada García-Moral:
  Direct control with radial basis function networks: Stability analysis and applications. 583-596
  
• Miguel Ayala Botto, José Sá da Costa:
  A comparison of nonlinear predictive control techniques using neural network models. 597-616
  
• Drasko Furundzic, Miodrag Djordjevic, Ana Jovicevic Bekic:
  Neural networks approach to early breast cancer detection. 617-633
  
• Emilia I. Barakova, Lambert Spaanenburg:
  Windowed active sampling for reliable neural learning. 635-650
  

Volume 44, Numbers 9-10, June 1998

• Krishna M. Kavi, Ali R. Hurson:
  Design of cache memories for dataflow architecture. 657-674
  
• C. E. Prakash, Swami Manohar:
  Hardware architecture for voxelization-based volume rendering of unstructured grids. 675-690
  
• Mohan Kumar, Lalit M. Patnaik, B. Nag:
  Fault-tolerant message routing in the extended hypercube. 691-702
  
• Evgenia Smirni, Emilia Rosti, Lawrence W. Dowdy, Giuseppe Serazzi:
  A methodology for the evaluation of multiprocessor non-preemptive allocation policies. 703-721
  
• Jeong-Ki Kim, Jae-Woo Chang:
  Horizontally divided signature files on a parallel machine architecture. 723-735
  
• Jovan Djordjevic, Milo Tomasevic, Miroslav Bojovic, Veselin Potic, Sinisa Randjic:
  An operating system accelerator. 737-754
  
• Gi-Ho Park, Oh-Young Kwon, Tack-Don Han, Shin-Dug Kim, Sung-Bong Yang:
  Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors. 755-772
  
• Pedro Tabuenca, Pablo Sánchez, Eugenio Villar:
  An algorithm for clock cycle selection in behavioral synthesis. 773-786
  
• Nam-Kyu Lee, Sung-Bong Yang, Tack-Don Han, ShinDug Kirn:
  Modeling and performance analysis of dual head disk structure. 787-802
  
• Fabio Ancona, Rodolfo Zunino:
  Hypercube structures with high-connectivity supporting nodes. 803-814
  
• Pedro López, Rosa Alcover, José Duato, Luisa Zúnica:
  A cost-effective methodology for the evaluation of interconnection networks. 815-830
  

Volume 44, Number 11, August 1998

• Mohamed Ould-Khaoua, Lewis M. Mackenzie, Rob J. Sutherland:
  Alleviating channel bandwidth constraints in multicomputer networks. 837-848
  
• Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis:
  Executing tree routing algorithms on a high-performance pattern associative router. 849-866
  
• Gyungho Lee, Jinseok Kong:
  Prospects of distributed shared memory for reducing global traffic in shared-bus multiprocessors. 867-872
  
• A. T. M. Shafiqul Khalid, Mohammad S. Alam, Abdul Ahad S. Awwal:
  KH-map: A new way of representing the hypercube structure. 873-885
  
• José Ramón González de Mendívil, Federico Fariña, Carlos F. Alastruey, José Ramón Garitagoitia:
  A safe distributed deadlock resolution algorithm. 887-907
  
• Vimal K. Khanna:
  A suggested protocol for internet access on PSDNs. 909-912
  

Volume 44, Number 12, September 1998

• Kyoung-In Kwon, Songchun Moon:
  Semantic multigranularity locking and its performance in object-oriented database systems. 917-935
  
• Anjaneyulu Pasala, D. Janaki Ram:
  FlexiFrag: A design pattern for flexible file sharing in distributed collaborative applications. 937-954
  
• Wen-Tsung Chang, Chien-Chao Tseng, Wen-Kuang Chou:
  Petri net-based analysis on object assignment in distributed object-oriented systems. 955-970
  
• Sang-Kyoon Kim, Se-Myung Park, Jong Kook Lee, Hang Joon Kim:
  On-line recognition of Korean characters using ART neural network and hidden Markov model. 971-984
  
• Milorad B. Tosic, Mile K. Stojcev, Dejan M. Maksimovic, Goran L. Djordjevic:
  The asynchronous counterflow pipeline bit-serial multiplier. 985-1004
  

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