Journal of Systems Architecture, Volume 46

Volume 46, Number 1, January 2000

• Paul J. M. Havinga, Gerard J. M. Smit:
  Design techniques for low-power systems. 1-21
  
• Abdullah I. AlMojel, Tarek A. El-Ghazawi, Thomas L. Sterling:
  Characterizing and representing workloads for parallel computer architectures. 23-37
  
• Andreas A. Veglis, Andreas S. Pombortsis, Efstathios Papaefstathiou:
  Performance evaluation of a bus-based multistage multiprocessor architecture. 39-47
  
• Charlie McElhone, Alan Burns:
  Scheduling optional computations for adaptive real-time systems. 49-77
  
• Alexander Romanovsky:
  Extending conventional languages by distributed/concurrent exception resolution. 79-95
  
• S. Bhattacharya, M. Nasipuri:
  Traffic analysis in a double grain Dataflow array processor. 97-101
  

Volume 46, Number 2, January 2000

• Marco Ajmone Marsan, Fabio Neri, C. Scarpati Cioffari, A. Vasco:
  GSPN models of bridged LAN configurations. 105-130
  
• S. K. Kwon, Hyoung-Goo Jeon, Kyoung-Rok Cho:
  Optimum reserved resource allocation scheme for handoff in CDMA cellular system. 131-144
  
• Antonio Puliafito, Orazio Tomarchio, Lorenzo Vita:
  MAP: Design and implementation of a mobile agents' platform. 145-162
  
• Shiao-Li Tsao, Yueh-Min Huang, Jen-Wen Ding:
  Performance analysis of video storage server under initial delay bounds. 163-179
  
• Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
  A scheme for multiple on-chip signature checking for embedded SRAMS. 181-199
  
• Novruz M. Allahverdi, Sirzad S. Kahramanli, Kayhan Erciyes:
  A fault tolerant routing algorithm based on cube algebra for hypercube systems. 201-205
  

Volume 46, Number 3, January 2000

• Laurence Tianruo Yang, Zebo Peng:
  An improved register-transfer level functional partitioning approach for testability. 209-223
  
• Giacomo Buonanno, Franco Fummi, Donatella Sciuto:
  An extended-UIO-based method for protocol conformance testing. 225-242
  
• K. S. Loh, W. F. Wong:
  Multiple context multithreaded superscalar processor architecture. 243-258
  
• Youngsik Kim, Tack-Don Han, Shin-Dug Kim:
  Impact of the memory interface structure in the memory-processor integrated architecture for computer vision. 259-274
  
• László Szirmay-Kalos, Gábor Márton, Tibor Fóris, Tamás Horváth:
  Development of process visualization systems: An object-oriented approach. 275-296
  
• Ujjwal Maulik, Sanghamitra Bandyopadhyay, Siddhartha Bhattacharyya:
  Fault tolerant permutation mapping in multistage interconnection network. 297-300
  

Volume 46, Number 4, January 2000

• Alan Burns, Divya Prasad, Andrea Bondavalli, Felicita Di Giandomenico, Krithi Ramamritham, John A. Stankovic, Lorenzo Strigini:
  The meaning and role of value in scheduling flexible real-time systems. 305-325
  
• Giuseppe Lipari, Giorgio C. Buttazzo:
  Schedulability analysis of periodic and aperiodic tasks with resource constraints. 327-338
  
• Friedhelm Stappert, Peter Altenbernd:
  Complete worst-case execution time analysis of straight-line hard real-time programs. 339-355
  
• José V. Busquets-Mataix, Daniel Gil, Pedro J. Gil, Andy J. Wellings:
  Techniques to increase the schedulable utilization of cache-based preemptive real-time systems. 357-378
  
• Anastasio Molano, Ángel Viña, Ragunathan Rajkumar:
  Operating system support for the management of hard real-time disk traffic. 379-395
  
• S. H. Son:
  Issues and approaches to supporting timeliness and security in real-time database systems. 397-410
  

Volume 46, Number 5, March 2000

• D. Venkatesulu, Timothy A. Gonsalves, R. K. Hariram:
  On the performance of distributed objects. 411-428
  
• Davide Anguita, Andrea Boni, Giancarlo Parodi:
  A case study of a distributed high-performance computing system for neurocomputing. 429-438
  
• Jih-Kwon Peir, Windsor W. Hsu, Honesty C. Young, Shauchi Ong:
  Improving cache performance with Full-Map Block Directory. 439-454
  
• D. De Almeida, Patrick Kellert:
  Markovian and analytical models for multiple bus multiprocessor systems with memory blockings. 455-477
  

Volume 46, Number 6, April 2000

• James Aweya:
  On the design of IP routers Part 1: Router architectures. 483-511
  
• Abdullah Al-Shoshan, Mohammad A. Aloqeely:
  Systolic arrays architecture for computing the time-frequency spectrum. 513-517
  
• Dajin Wang:
  The diagnosability of hypercubes with arbitrarily missing links. 519-527
  
• Nabanita Das, Krishnendu Mukhopadhyaya, Jayasree Dattagupta:
  O(n) routing in rearrangeable networks. 529-542
  
• Hai Jin, Kai Hwang:
  Stripped mirroring RAID architecture. 543-550
  

Volume 46, Number 7, April 2000

• Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
  Low power architectures for digital signal processing. 551-571
  
• Kam-yiu Lam, Joseph Kee-Yin Ng:
  A conditional abortable priority ceiling protocol for scheduling mixed real-time tasks. 573-585
  
• A. Castorino, Gianfranco Ciccarella:
  Algorithms for real-time scheduling of error-cumulative tasks based on the imprecise computation approach. 587-600
  
• Rodrigo M. Santos, Jorge Santos, Javier Orozco, M. Zambón:
  Real-time multimedia standards in DQDB. 601-605
  
• Nicolas Navet, Y.-Q. Song, Françoise Simonot:
  Worst-case deadline failure probability in real-time applications distributed over controller area network. 607-617
  
• Humayun Khalid:
  Validation of SPEC6^TM CFP95 traces for accurate performance evaluation of computer systems. 619-623
  

Volume 46, Number 8, May 2000

• Andy M. Tyrrell, Stephen L. Smith:
  Heterogeneous distributed and parallel architectures: Hardware, software and design tools. 625-626
  
• Howard Jay Siegel, Shoukat Ali:
  Techniques for mapping tasks to machines in heterogeneous computing systems. 627-639
  
• Andrea Clematis, Gabriella Dodero, Vittoria Gianuzzi:
  Efficient use of parallel libraries on heterogeneous Networks of Workstations. 641-653
  
• Jeong-Ki Kim, Jae-Woo Chang:
  Vertically-partitioned parallel signature file method. 655-673
  
• Patricia González, José Carlos Cabaleiro, Tomás F. Pena:
  On parallel solvers for sparse triangular systems. 675-685
  
• Kyungcheol Sohn, Songchun Moon:
  Achieving high degree of concurrency in multidatabase transaction scheduling: MTOS. 687-698
  
• Inhwan Jung, Sonchung Moon:
  Transaction multicasting scheme for resilient routing control in parallel cluster database systems. 699-719
  

Volume 46, Number 9, July 2000

• Andreas Steininger:
  Testing and built-in self-test - A survey. 721-747
  
• S. J. Davis, C. J. Elston, P. A. Findlay:
  Register bypassing in an asynchronous superscalar processor. 749-764
  
• Dongho Yoo, Inyoung Park, Seung Ryoul Maeng:
  Multistage ring network: An interconnection network for large scale shared memory multiprocessors. 765-778
  
• Mohamed Ould-Khaoua, Lewis M. Mackenzie:
  On the design of hypermesh interconnection networks for multicomputers. 779-792
  
• Anita Mittal, G. Manimaran, C. Siva Ram Murthy:
  Integrated dynamic scheduling of hard and QoS degradable real-time tasks in multiprocessor systems. 793-807
  
• Yousef J. Al-Houmaily, Panos K. Chrysanthis:
  An atomic commit protocol for gigabit-networked distributed database systems. 809-833
  

Volume 46, Number 10, July 2000

• Jacques Chassin de Kergommeaux, Alain Fagot:
  Execution replay of parallel procedural programs. 835-849
  
• Mayez A. Al-Mouhamed, Adel Al-Massarani:
  Scheduling optimization through iterative refinement. 851-871
  
• José L. Sánchez, José M. García:
  Dynamic reconfiguration of node location in wormhole networks. 873-888
  
• Sukhoon Kang, Songchun Moon:
  Read-down conflict-preserving serializability as a correctness criterion for multilevel-secure optimistic concurrency control: CSR/RD. 889-902
  
• Yunseok Rhee, Joonwon Lee:
  Broadcast directory: A scalable cache coherent architecture for mesh-connected multiprocessors. 903-918
  
• Tzung-Shi Chen, Chih-Yung Chang, Jang-Ping Sheu:
  Efficient path-based multicast in wormhole-routed mesh networks. 919-930
  
• Francisco J. Suárez, Daniel F. García, Javier García:
  Measurement based analysis of temporal behaviour as support for scheduling problems in parallel and distributed real-time systems. 931-949
  
• Gopal Racherla, Sridhar Radhakrishnan, L. S. DeBrunner:
  Parameterization of efficient dynamic reconfigurable trees. 951-954
  

Volume 46, Number 11, September 2000

• Pasi Kolinummi, Timo Hämäläinen, Jukka Saarinen:
  Chained backplane communication architecture for scalable multiprocessor systems. 955-972
  
• Stefanos Kaxiras:
  Distributed vector architectures. 973-990
  
• Rômulo Silva de Oliveira, Joni da Silva Fraga:
  Fixed priority scheduling of tasks with arbitrary precedence constraints in distributed hard real-time systems. 991-1004
  
• Hyojeong Song, Boseob Kwon, Ikhyeon Jang, Hyunsoo Yoon:
  An output queueing analysis of multipath ATM switches. 1005-1012
  
• Humayun Khalid:
  Performance evaluation of system architectures with validated input data. 1013-1017
  
• Manuel P. Malumbres, José Duato:
  An efficient implementation of tree-based multicast routing for distributed shared-memory multiprocessors. 1019-1032
  
• Heiko Oehring, Ulrich Sigmund, Theo Ungerer:
  Performance of simultaneous multithreaded multimedia-enhanced processors for MPEG-2 video decompression. 1033-1046
  
• Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu:
  Efficient module selections for finding highly acceptable designs based on inclusion scheduling. 1047-1071
  

Volume 46, Number 12, October 2000

• H. Moharam, M. A. Abd El-Baky, S. M. M. Nassar:
  YOMNA - An efficient deadlock-free multicast wormhole algorithm in 2-D mesh multicomputers. 1073-1091
  
• Ando Ki, Alan E. Knowles:
  Stride prefetching for the secondary data cache. 1093-1102
  
• Samia Loucif, Mohamed Ould-Khaoua:
  On the relative performance merits of hypercube and hypermesh networks. 1103-1114
  
• Wen-Fong Wang, Wen-Shyang Hwang, Jun-Yao Wang:
  Design of a large-scale Gbit/s MAN using a cyclic reservation-based MAC protocol. 1115-1135
  
• Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
  Symbolic forward/backward traversals of large finite state machines. 1137-1158
  

Volume 46, Number 13, November 2000

• Ridha Djemal, Guy Mazaré, Rached Tourki:
  Rapid prototyping of an ATM programmable associative operator. 1159-1173
  
• Gail-Joon Ahn:
  Role-based access control in DCOM. 1175-1184
  
• Huiwei Guan, To-Yat Cheung:
  Efficient approaches for constructing a massively parallel processing system. 1185-1190
  
• Inbum Jung, Jongwoong Hyun, Joonwon Lee:
  A scheduling policy for preserving cache locality in a multiprogrammed system. 1191-1204
  
• Vladimir Vlassov, Rassul Ayani:
  Analytical modeling of multithreaded architectures. 1205-1230
  
• Toshinori Sato:
  Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism. 1231-1252
  
• Ioannis E. Pountourakis:
  Optimal bandwidth allocation and stability of high-speed networks for CSMA/CD protocols. 1253-1256
  
• A. K. Bandyopadhyay, J. Bandyopadhyay:
  On the derivation of a correct deadlock free communication kernel for loop connected message passing architecture from its user's specification. 1257-1261
  

Volume 46, Number 14, December 2000

• Sri Parameswaran, Matthew F. Parkinson, Peter L. Bartlett:
  Profiling in the ASP codesign environment. 1263-1274
  
• D. Vidya, Ranjani Parthasarathy, T. C. Bina, N. G. Swaroopa:
  Architecture for fractal image compression. 1275-1291
  
• Won-Kee Hong, Shin-Dug Kim:
  A section cache system designed for VLIW architectures. 1293-1308
  
• Andrew Bardsley, Doug A. Edwards:
  Synthesising an asynchronous DMA controller with Balsa. 1309-1319
  
• Wolfgang Günther, Rolf Drechsler:
  ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs. 1321-1334
  
• Vimal K. Khanna:
  A novel approach for implementing high-speed and long-distance networking protocols in a limited memory embedded kernel. 1335-1348
  
• Muhammet Fikret Ercan, Yu-Fai Fung, M. Suleyman Demokan:
  Communication in a multi-layer MIMD system for computer vision. 1349-1364
  

Volume 46, Number 15, December 2000

• Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim:
  An on-chip cache compression technique to reduce decompression overhead and design complexity. 1365-1382
  
• Nam-Kyu Lee, Sung-Bong Yang, Kyoung-Woo Lee:
  Efficient parity placement schemes for tolerating up to two disk failures in disk arrays. 1383-1402
  
• JaeHo Jeon, Hyung-Sun Kim, GeonYoung Choi, HyunWook Park:
  KAIST image computing system (KICS): A parallel architecture for real-time multimedia data processing. 1403-1418
  
• Giacomo Cabri, Letizia Leonardi, Franco Zambonelli:
  Agents for information retrieval: Issues of mobility and coordination. 1419-1433
  
• Pao-Ann Hsiung:
  Embedded software verification in hardware-software codesign. 1435-1450
  
• Jung-Hoon Lee, Jang-Soo Lee, Shin-Dug Kim:
  A new cache architecture based on temporal and spatial locality. 1451-1467
  
• Lieven Eeckhout, Henk Neefs, Koen De Bosschere:
  Early design stage exploration of fixed-length block structured architectures. 1469-1486
  

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