Volume 56,
Number 1,
January 2010
- Yuan-Shin Hwang, Jia-Jhe Li:
On reducing load/store latencies of cache accesses.
1-15
- Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Partha P. Maji:
An analytical performance model for the Spidergon NoC with virtual channels.
16-26
- Young-Ho Seo, Hyun-Jun Choi, Ji-Sang Yoo, Dong-Wook Kim:
An architecture of a high-speed digital hologram generator based on FPGA.
27-37
- Claudio Brunelli, Fabio Garzia, Davide Rossi, Jari Nurmi:
A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations.
38-47
- George Kornaros:
A soft multi-core architecture for edge detection and data analysis of microarray images.
48-62
- Manel Velasco, Pau Martí, Josep M. Fuertes, Camilo Lozoya, Scott A. Brandt:
Experimental evaluation of slack management in real-time control systems: Coordinated vs. self-triggered approach.
63-74
Erratum
- Gyungho Lee, Yixin Shi:
Erratum to "Access region cache with register guided memory reference partitioning" [Journal of Systems Architecture 55 (2009) 434-445].
75
Volume 56,
Numbers 2-3,
February-March 2010
- Alberto Ros, Manuel E. Acacio, José M. García:
A scalable organization for distributed directories.
77-87
- Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen:
UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems.
88-102
- Sebastian Lange, Martin Middendorf:
Multi-level reconfigurable architectures in the switch model.
103-115
- Jason Van Dyken, José G. Delgado-Frias:
FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm.
116-123
- Matthew Areno, Brandon Eames, Joshua Templin:
A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs.
124-135
- Keoncheol Shin, Hwansoo Han, Kwang-Moo Choe:
Composition-based Cache simulation for structure reorganization.
136-149
Volume 56,
Numbers 4-6,
April - June 2010
Volume 56,
Number 7,
July 2010
- Juan Antonio Gómez Pulido:
From systems to networks on chip: A promising research area in the Hardware/Software co-design.
221-222
- Sébastien Le Beux, Guy Bois, Gabriela Nicolescu, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin:
Combining mapping and partitioning exploration for NoC-based embedded systems.
223-232
- Ser-Hoon Lee, Yeo-Chan Yoon, Sun-Young Hwang:
Communication-aware task assignment algorithm for MPSoC using shared memory.
233-241
- Amit Kumar Singh, Thambipillai Srikanthan, Akash Kumar, Wu Jigang:
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms.
242-255
- Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi:
EDXY - A low cost congestion-aware routing algorithm for network-on-chips.
256-264
- Ahsan Shabbir, Akash Kumar, Sander Stuijk, Bart Mesman, Henk Corporaal:
CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications.
265-277
- Mouna Baklouti, Yassine Aydi, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA.
278-292
- Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Reconfigurable Networks on Chip: DRNoC architecture.
293-302
Volume 56,
Number 8,
August 2010
- Juan Antonio Gómez Pulido:
Recent advances in Hardware/Software co-design.
303-304
- Afandi Ahmad, Benjamin Krill, Abbes Amira, Hassan Rabah:
Efficient architectures for 3D HWT using dynamic partial reconfiguration.
305-316
- Usman Ali, Mohammad Bilal Malik:
Hardware/software co-design of a real-time kernel based tracking system.
317-326
- Alejandro Castillo Atoche, Deni Torres Román, Yuriy Shkvarko:
Towards real time implementation of reconstructive signal processing algorithms using systolic arrays coprocessors.
327-339
- Tao Li, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu:
Selecting profitable custom instructions for reconfigurable processors.
340-351
- Da-Ren Chen, Chiun-Chieh Hsu, You-Shyang Chen, Chi-Jung Kuo, Lin-Chih Chen:
Transition-aware DVS algorithm for real-time systems using tree structure analysis.
352-367
- Jonghee M. Youn, Minwook Ahn, Yunheung Paek, Jongwung Kim, Jeonghun Cho:
Two versions of architectures for dynamic implied addressing mode.
368-383
- Chen Fu, Dongxin Wen, Xiaoqun Wang, Xiao-Zong Yang:
Hardware transactional memory: A high performance parallel programming model.
384-391
- Quentin L. Meunier, Frédéric Pétrot, Jean-Louis Roch:
Hardware/software support for adaptive work-stealing in on-chip multiprocessor.
392-406
Volume 56,
Number 9,
September 2010
- Luis Morales-Velazquez, René de Jesús Romero-Troncoso, Roque Alfredo Osornio-Rios, Gilberto Herrera Ruiz, Eduardo Cabal-Yepez:
Open-architecture system based on a reconfigurable hardware-software multi-agent platform for CNC machines.
407-418
- Jong Wook Kwak, Young Tae Jeon:
Compressed tag architecture for low-power embedded cache systems.
419-428
- Antonio Flores, Manuel E. Acacio, Juan L. Aragón:
Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs.
429-441
- Mauricio Vanegas, Matteo Tomasi, Javier Díaz, Eduardo Ros Vidal:
Multi-port abstraction layer for FPGA intensive memory exploitation applications.
442-451
- Minghua Tang, Xiaola Lin:
Quarter Load Threshold (QLT) flow control for wormhole switching in mesh-based Network-on-Chip.
452-462
- Jianguo Yao, Xue Liu, Zonghua Gu, Xiaorui Wang, Jian Li:
Online adaptive utilization control for real-time embedded multiprocessor systems.
463-473
- Yosi Ben-Asher, Nadav Rotem, Eddie Shochat:
Finding the best compromise in compiling compound loops to Verilog.
474-486
Volume 56,
Number 10,
October 2010
- Bhanu Pisupati, Geoffrey Brown:
Embedded software debugging using virtual filesystem abstractions.
487-499
- Haibing Guan, Bo Liu, Zhengwei Qi, Yindong Yang, Hongbo Yang, Alei Liang:
CoDBT: A multi-source dynamic binary translator using hardware-software collaborative techniques.
500-508
- Kristoffer Nyborg Gregertsen, Amund Skavhaug:
Implementing the new Ada 2005 timing event and execution time control features on the AVR32 architecture.
509-522
- Hongzhen Xu, Guosun Zeng:
Specification and verification of dynamic evolution of software architectures.
523-533
- Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan, Xiaowei Li:
Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling.
534-542
Volume 56,
Number 11,
November 2010
- Ignacio Bravo, Marco D. Santambrogio:
Design flows and system architectures for adaptive computing on reconfigurable platforms.
543-544
- Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen:
Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption.
545-560
- Sven-Ole Voigt, Malte Baesler, Thomas Teufel:
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing.
561-576
- Matteo Tomasi, Francisco Barranco, Mauricio Vanegas, Javier Díaz, Eduardo Ros Vidal:
Fine grain pipeline architecture for high performance phase-based optical flow computation.
577-587
- Roberto Gutierrez, V. Torres, Javier Valls-Coquillat:
FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques.
588-596
- Balal Ahmad, Ali Ahmadinia, Tughrul Arslan:
High level modeling and automated generation of heterogeneous SoC architectures with optimized custom reconfigurable cores and on-chip communication media.
597-615
- Jose Brizuela, Alberto Ibañez, Carlos Fritsch:
NDE system for railway wheel inspection in a standard FPGA.
616-622
- Mahmood Fazlali, Mojtaba Sabeghi, Ali Zakerolhosseini, Koen Bertels:
Efficient task scheduling for runtime reconfigurable systems.
623-632
- César Pedraza, Emilio Castillo, Javier Castillo, José Luis Bosque, José Ignacio Martínez, Oscar David Robles, Javier Cano, Pablo Huerta:
Content-based image retrieval algorithm acceleration in a low-cost reconfigurable FPGA cluster.
633-640
Volume 56,
Number 12,
December 2010
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