Volume 58, Number 1, January 2012
Volume 58, Number 2, February 2012
Volume 58, Numbers 3-4, March 2012
- Tse-Chen Yeh, Ming-Chao Chiang:
On the interfacing between QEMU and SystemC for virtual platform construction: Using DMA as a case.
99-111
- Mostafa E. Salehi, Sied Mehdi Fakhraie, Amir Yazdanbakhsh:
Instruction set architectural guidelines for embedded packet-processing engines.
112-125
- Francisco Triviño, José L. Sánchez, Francisco J. Alfaro, José Flich:
Network-on-Chip virtualization in Chip-Multiprocessor Systems.
126-139
- Salih Bayar, Arda Yurdakul:
A dynamically reconfigurable communication architecture for multicore embedded systems.
140-159
- Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir, Oguz Tosun:
Reliability-aware core partitioning in chip multiprocessors.
160-176
Volume 58, Number 5, April 2012
- Daniela Cancila, Huáscar Espinoza, Richard F. Paige:
Special issue on Model Based Engineering for Embedded Systems Design.
177
- Imran Rafiq Quadri, Abdoulaye Gamatié, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser:
Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives.
178-194
- Éamonn Linehan, Siobhán Clarke:
An aspect-oriented, model-driven approach to functional hardware verification.
195-208
- Tero Arpinen, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen:
MARTE profile extension for modeling dynamic power management of embedded systems.
209-219
Volume 58, Numbers 6-7, June - August 2012
- Duck-Ho Bae, Ji-Woong Chang, Sang-Wook Kim:
An efficient method for record management in flash memory environment.
221-232
- Woochul Kang, Sang Hyuk Son:
Power- and time-aware buffer cache management for real-time embedded databases.
233-246
- Ivan Gonzalez, Sergio López-Buedo, Gustavo Sutter, Diego Sanchez-Roman, Francisco J. Gomez-Arribas, Javier Aracil:
Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture.
247-256
- Patricia López Martínez, César Cuevas, José M. Drake:
Compositional real-time models.
257-276
Volume 58, Number 8, September 2012
- F. Javier Toledo-Moreo, J. Javier Martínez-Álvarez, F. Javier Garrigós-Guerrero, José Manuel Ferrández-Vicente:
FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size.
277-285
- Mario G. C. A. Cimino, Francesco Marcelloni:
An efficient model-based methodology for developing device-independent mobile applications.
286-304
- Haibing Guan, Erzhou Zhu, Hongxi Wang, Ruhui Ma, Yindong Yang, Bin Wang:
SINOF: A dynamic-static combined framework for dynamic binary translation.
305-317
- Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton, Yvon Trinquet:
Harmless, a hardware architecture description language dedicated to real-time embedded system simulation.
318-337
- Hongzhen Xu, Guosun Zeng:
Retraction notice to ''Specification and Verification of Dynamic Evolution of Software Architectures" [SYSARC 56 (10) (2010) 523-533].
338
Volume 58, Number 9, October 2012
Volume 58, Number 10, November 2012
- Vivek Chaturvedi, Huang Huang, Shangping Ren, Gang Quan:
On the fundamentals of leakage aware real-time DVS scheduling for peak temperature minimization.
387-397
- Yaodong Wang, Guozhen Tan, Yuan Wang, Yong Yin:
Perceptual control architecture for cyber-physical systems in traffic incident management.
398-411
- Ming Chen, Xiaorui Wang, Hairong Qi, Mallikarjun Shankar:
Adaptive response time control for metadata matching in information dissemination systems.
412-425
- Daigu Zhang, Xiaofeng Liao, Meikang Qiu, Jingtong Hu, Edwin Hsing-Mean Sha:
Randomized execution algorithms for smart cards to resist power analysis attacks.
426-438
- Meikang Qiu, Zhong Ming, Jiayin Li, Shaobo Liu, Bin Wang, Zhonghai Lu:
Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors.
439-445
Last update Mon May 20 18:07:08 2013
CET by the DBLP Team — 
Data released under the ODC-BY 1.0 license — See also our legal information page
