IEEE Journal of Solid-State Circuits, Volume 46

Volume 46, Number 1, January 2011

• Christoph Studer, Christian Benkeser, Sandro Belfanti, Quiting Huang:
  Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE. 8-17
  
• David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David Blaauw:
  A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation. 18-31
  
• Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki:
  A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. 32-41
  
• Seungjin Lee, Jinwook Oh, Junyoung Park, Joonsoo Kwon, Minsu Kim, Hoi-Jun Yoo:
  A 345 mW Heterogeneous Many-Core Processor With an Intelligent Inference Engine for Robust Object Recognition. 42-51
  
• Guido De Sandre, Luca Bettini, Alessandro Pirola, Lionel Marmonier, Marco Pasotti, Massimo Borghi, Paolo Mattavelli, Paola Zuliani, Luca Scotti, Gianfranco Mastracchio, Ferdinando Bedeschi, Roberto Gastaldi, Roberto Bez:
  A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology. 52-63
  
• John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Caon:
  A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. 64-75
  
• Pramod Kolar, Eric Karl, Uddalak Bhattacharya, Fatih Hamzaoglu, Henry Nho, Yong-Gee Ng, Yih Wang, Kevin Zhang:
  A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation. 76-84
  
• Masood Qazi, Kevin Stawiasz, Leland Chang, Anantha P. Chandrakasan:
  A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS. 85-96
  
• Changhyuk Lee, Sok-Kyu Lee, Sunghoon Ahn, Jinhaeng Lee, Wonsun Park, Yongdeok Cho, Chaekyu Jang, Chulwoo Yang, Sanghwa Chung, In-Suk Yun, Byoungin Joo, Byoungkwan Jeong, Jeeyul Kim, Jeakwan Kwon, Hyunjong Jin, Yujong Noh, Jooyun Ha, Moonsoo Sung, Daeil Choi, Sanghwan Kim, Jeawon Choi, Taeho Jeon, Heejoung Park, Joong-Seob Yang, Yo-Hwan Koh:
  A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS. 97-106
  
• Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun:
  A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. 107-118
  
• Nasser A. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, Praveen Mosalikanti, Timothy M. Wilson, Ali M. El-Husseini, Mark Neidengard, Ramy E. Aly, Mahadev Nemani, Muntaquim Chowdhury, Rajesh Kumar:
  A Family of 32 nm IA Processors. 119-130
  
• Jinuk Luke Shin, Dawei Huang, Bruce Petrick, Changku Hwang, Kenway Tam, Alan Smith, Ha Pham, Hongping Li, Timothy Johnson, Francis Schumacher, Ana Sonia Leon, Allan Strong:
  A 40 nm 16-Core 128-Thread SPARC SoC Processor. 131-144
  
• Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban:
  POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. 145-161
  
• Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, A. Novak, Sam Naffziger:
  An x86-64 Core in 32 nm SOI CMOS. 162-172
  
• Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart:
  A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. 173-183
  
• Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar:
  Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. 184-193
  
• Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De:
  A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. 194-208
  
• Refet Firat Yazicioglu, Sunyoung Kim, Tom Torfs, Hyejung Kim, Chris Van Hoof:
  A 30 μ W Analog Signal Processor ASIC for Portable Biopotential Signal Monitoring. 209-223
  
• Hossein Miri Lavasani, Wanling Pan, Brandon Harrington, Reza Abdolvand, Farrokh Ayazi:
  A 76 dB Ω 1.7 GHz 0.18 μ m CMOS Tunable TIA Using Broadband Current Pre-Amplifier for High Frequency Lateral MEMS Oscillators. 224-235
  
• Youngcheol Chae, Jimin Cheon, Seunghyun Lim, Minho Kwon, Kwisung Yoo, Wunki Jung, Dong-Hun Lee, Seogheon Ham, Gunhee Han:
  A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel Delta Sigma ADC Architecture. 236-247
  
• David Stoppa, Nicola Massari, Lucio Pancheri, Mattia Malfatti, Matteo Perenzoni, Lorenzo Gonzo:
  A Range Image Sensor Based on 10- μħbox m Lock-In Pixels in 0.18- μ m CMOS Imaging Technology. 248-258
  
• Christoph Posch, Daniel Matolin, Rainer Wohlgenannt:
  A QVGA 143 dB Dynamic Range Frame-Free PWM Image Sensor With Lossless Pixel-Level Video Compression and Time-Domain CDS. 259-275
  
• Hagen Marien, Michiel Steyaert, Erik van Veenendaal, Paul Heremans:
  A Fully Integrated Delta Sigma ADC in Organic Thin-Film Transistor Technology on Flexible Plastic Foil. 276-284
  
• Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
  User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects. 285-292
  
• Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal:
  Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. 293-307
  
• Matthew Spencer, Fred Chen, Cheng C. Wang, Rhesa Nathanael, Hossein Fariborzi, Abhinav Gupta, Hei Kam, Vincent Pott, Jaeseok Jeon, Tsu-Jae King Liu, Dejan Markovic, Elad Alon, Vladimir Stojanovic:
  Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications. 308-320
  
• Kunal Paralikar, Peng Cong, Ofer Yizhar, Lief Ericsson Fenno, Wesley Santa, Chris Nielsen, David Dinsmoor, Bob Hocken, Gordon Munns, Jon Giftakis, Karl Deisseroth, Timothy Denison:
  An Implantable Optical Stimulation Delivery System for Actuating an Excitable Biosubstrate. 321-332
  
• Yogesh K. Ramadass, Anantha P. Chandrakasan:
  A Battery-Less Thermoelectric Energy Harvesting Interface Circuit With 35 mV Startup Voltage. 333-341
  
• Nan Sun, Tae-Jong Yoon, Hakho Lee, William Andress, Ralph Weissleder, Donhee Ham:
  Palm NMR and 1-Chip NMR. 342-352
  
• Long Yan, Joonsung Bae, Seulki Lee, Taehwan Roh, Kiseok Song, Hoi-Jun Yoo:
  A 3.9 mW 25-Electrode Reconfigured Sensor for Wearable Cardiac Monitoring System. 353-364
  

Volume 46, Number 2, February 2011

• Wuttichai Lerdsitsomboon, K. O. Kenneth:
  Technique for Integration of a Wireless Switch in a 2.4 GHz Single Chip Radio. 368-377
  
• Lei Zhou, Chun-Cheng Wang, Zhiming Chen, Payam Heydari:
  A W-band CMOS Receiver Chipset for Millimeter-Wave Radiometer Systems. 378-391
  
• Deyi Pi, Byung-Kwan Chun, Payam Heydari:
  A Synthesis-Based Bandwidth Enhancement Technique for CMOS Amplifiers: Theory and Design. 392-402
  
• Imran Bashir, Robert Bogdan Staszewski, Oren Eliezer, Bhaskar Banerjee, Poras T. Balsara:
  A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter. 403-415
  
• Qiang Zhu, Yang Xu:
  A 228 μ W 750 MHz BPSK Demodulator Based on Injection Locking. 416-423
  
• Heesoo Song, Deok-Soo Kim, Do-Hwan Oh, Suhwan Kim, Deog-Kyoon Jeong:
  A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control. 424-434
  
• Young-Sang Kim, Seon-Kyoo Lee, Hong-June Park, Jae-Yoon Sim:
  A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL. 435-444
  
• Xiaohong Peng, Willy Sansen, Ligang Hou, Jinhui Wang, Wuchen Wu:
  Impedance Adapting Compensation for Low-Power Multistage Amplifiers. 445-451
  
• Song Guo, Hoi Lee:
  Dual Active-Capacitive-Feedback Compensation for Low-Power Large-Capacitive-Load Three-Stage Amplifiers. 452-464
  
• Luca Magnelli, Felice Crupi, Pasquale Corsonello, Calogero Pace, Giuseppe Iannaccone:
  A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference. 465-474
  
• Johan Borg, Jonny Johansson:
  An Ultrasonic Transducer Interface IC With Integrated Push-Pull 40 Vpp, 400 mA Current Output, 8-bit DAC and Integrated HV Multiplexer. 475-484
  
• Yashodhan Moghe, Torsten Lehmann, Tim Piessens:
  Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 μ m HV-CMOS Technology. 485-497
  
• Eleonora Franchi Scarselli, Antonio Gnudi, Federico Natali, Mauro Scandiuzzo, Roberto Canegallo, Roberto Guerrieri:
  Automatic Compensation of the Voltage Attenuation in 3-D Interconnection Based on Capacitive Coupling. 498-506
  
• Po-Tsang Huang, Wei Hwang:
  A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. 507-519
  
• Meng-Fan Chang, Shi-Wei Chang, Po-Wei Chou, Wei-Cheng Wu:
  A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications. 520-529
  
• Daisaburo Takashima, Yasushi Nagadomi, Kosuke Hatsuda, Yohji Watanabe, Shuso Fujii:
  A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance. 530-536
  
• Ming-Dou Ker, Wen-Yi Chen, Wuu-Trong Shieh, I.-Ju Wei:
  Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs. 537-545
  
• Alberto Pirola, Antonio Liscidini, Rinaldo Castello:
  Corrections to "Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping" [Sep 10 1770-1780]. 546
  

Volume 46, Number 3, March 2011

• Federico Vecchi, Stefano Bozzola, Enrico Temporiti, Davide Guermandi, Massimo Pozzoni, Matteo Repossi, Marco Cusmai, Ugo Decanis, Andrea Mazzanti, Francesco Svelto:
  A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS. 551-561
  
• Desheng Ma, Fa Foster Dai, Richard C. Jaeger, J. David Irwin:
  An X- and Ku-Band Wideband Recursive Receiver MMIC With Gain-Reuse. 562-571
  
• Masaki Kitsunezuka, Takashi Tokairin, Tadashi Maeda, Muneo Fukaishi:
  A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme. 572-582
  
• Omeed Momeni, Ehsan Afshari:
  High Power Terahertz and Millimeter-Wave Oscillator Design: A Systematic Approach. 583-597
  
• Shih-An Yu, Yves Baeyens, Joseph Weiner, Ut-Va Koc, Marta Rambaud, Fang-Ren Liao, Young-Kai Chen, Peter R. Kinget:
  A Single-Chip 125-MHz to 32-GHz Signal Source in 0.18- μ m SiGe BiCMOS. 598-614
  
• Pin-En Su, Sudhakar Pamarti:
  A 2.4 GHz Wideband Open-Loop GFSK Transmitter With Phase Quantization Noise Cancellation. 615-626
  
• Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
  A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation. 627-638
  
• Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz:
  A Continuous Time Multi-Bit Delta Sigma ADC Using Time Domain Quantizer and Feedback Element. 639-650
  
• Seon-Kyoo Lee, Seung-Jin Park, Hong-June Park, Jae-Yoon Sim:
  A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface. 651-659
  
• Mohammad Taherzadeh-Sani, Anas A. Hamoui:
  A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS. 660-668
  
• Jorge Fernandez-Berni, Ricardo Carmona-Galán, Luis Carranza-González:
  FLIP-Q: A QCIF Resolution Focal-Plane Array for Low-Power Image Processing. 669-680
  
• Daisaburo Takashima, Yasushi Nagadomi, Tohru Ozaki:
  A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell. 681-689
  
• Myoung Jin Lee:
  A Sensing Noise Compensation Bit Line Sense Amplifier for Low Voltage Applications. 690-694
  
• Cheng-Hung Lo, Shi-Yu Huang:
  P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation. 695-704
  
• David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David Blaauw:
  Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation". 705
  

Volume 46, Number 4, April 2011

• Srinivasa R. Sridhara, Michael DiRenzo, Srinivas Lingam, Seok-Jun Lee, Ra Blazquez, Jay Maxey, Samer Ghanem, Yu-Hung Lee, Rami A. Abdallah, Prashant Singh, Manish Goel:
  Microwatt Embedded Processor Platform for Medical System-on-Chip Applications. 721-730
  
• Meysam Azin, David J. Guggenmos, Scott Barbay, Randolph J. Nudo, Pedram Mohseni:
  A Battery-Powered Activity-Dependent Intracortical Microstimulation IC for Brain-Machine-Brain Interface. 731-745
  
• Jose L. Bohorquez, Marcus Yip, Anantha P. Chandrakasan, Joel L. Dawson:
  A Biomedical Sensor Interface With a sinc Filter and Interference Cancellation. 746-756
  
• Praveen Salihundam, Shailendra Jain, Tiju Jacob, Shasi Kumar, Vasantha Erraguntla, Yatin Hoskote, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar:
  A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS. 757-766
  
• Sanu Mathew, Farhana Sheikh, Michael E. Kounavis, Shay Gueron, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark Anders, Ram Krishnamurthy:
  53 Gbps Native GF(2 ⁴) ² Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors. 767-776
  
• Dajiang Zhou, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, Satoshi Goto:
  A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip. 777-788
  
• Takushi Hashida, Makoto Nagata:
  An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration. 789-796
  
• Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De:
  Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. 797-805
  
• Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi:
  Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. 806-814
  
• Jui-Jen Wu, Yen-Hui Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi:
  A Large Sigma V _TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme. 815-827
  
• Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa:
  1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. 828-837
  
• Manar El-Chammas, Boris Murmann:
  A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration. 838-847
  
• Chun-Cheng Huang, Chung-Yi Wang, Jieh-Tsorng Wu:
  A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques. 848-858
  
• Chun C. Lee, Michael P. Flynn:
  A SAR-Assisted Two-Stage Pipeline ADC. 859-869
  
• Hooman Darabi, Paul Chang, Henrik Jensen, Alireza Zolfaghari, Paul Lettieri, John C. Leete, Behnam Mohammadi, Janice Chiu, Qiang Li, Shr-Lung Chen, Zhimin Zhou, Morteza Vadipour, C. Chen, Yuyu Chang, Ahmad Mirzaei, Ahmad Yazdi, Mohammad Nariman, Amir Hadji-Abdolhamid, Ethan Chang, B. Zhao, Kevin Juan, Puneet Suri, C. Guan, L. Serrano, John Leung, J. Shin, J. Kim, H. Tran, P. Kilcoyne, H. Vinh, Eric Raith, M. Koscal, Ajat Hukkoo, C. Hayek, V. Rakhshani, Charlie Wilcoxson, Maryam Rofougaran, Ahmadreza Rofougaran:
  A Quad-Band GSM/GPRS/EDGE SoC in 65 nm CMOS. 870-882
  
• Akira Tanabe, Ken'ichiro Hijioka, Hirokazu Nagase, Yoshihiro Hayashi:
  A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5-20 GHz Tunable LC-VCO. 883-893
  
• Behzad Razavi:
  A 300-GHz Fundamental Oscillator in 65-nm CMOS Technology. 894-903
  
• Yu-Huei Lee, Yao-Yi Yang, Shih-Jung Wang, Ke-Horng Chen, Ying-Hsi Lin, Yi-Kuang Chen, Chen-Chih Huang:
  Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters With 91% Peak Efficiency. 904-915
  
• Michaël Pelissier, Joni Jantunen, Bertrand Gomez, Jarmo Arponen, Gilles Masson, Serigne Dia, Jaakko Varteva, Marjorie Gary:
  A 112 Mb/s Full Duplex Remotely-Powered Impulse-UWB RFID Transceiver for Wireless NV-Memory Applications. 916-927
  
• Joonsung Bae, Long Yan, Hoi-Jun Yoo:
  A Low Energy Injection-Locked FSK Transceiver With Frequency-to-Amplitude Conversion for Body Sensor Applications. 928-937
  
• Adam C. Heiberg, Thomas William Brown, Terri S. Fiez, Kartikeya Mayaram:
  A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS. 938-949
  
• Ahmad Mirzaei, Hooman Darabi, Ahmad Yazdi, Zhimin Zhou, Ethan Chang, Puneet Suri:
  A 65 nm CMOS Quad-Band SAW-Less Receiver SoC for GSM/GPRS/EDGE. 950-964
  
• Noriyuki Miura, Tsunaaki Shidei, Yuxiang Yuan, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda:
  A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme. 965-973
  
• Jared Zerbe, Barry Daly, Lei Luo, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi Kollipara:
  A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. 974-985
  
• Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa:
  An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration. 986-991
  

Volume 46, Number 5, May 2011

• Amir Ghaffari, Eric A. M. Klumperink, Michiel C. M. Soer, Bram Nauta:
  Tunable High-Q N-Path Band-Pass Filters: Modeling and Verification. 998-1010
  
• Shahriar Shahramian, Adam Hart, Alexander Tomkins, Anthony Chan Carusone, Patrice Garcia, Pascal Chevalier, Sorin P. Voinigescu:
  Design of a Dual W- and D-Band PLL. 1011-1022
  
• Yan-Yu Huang, Wangmyong Woo, Youngchang Yoon, Chang-Ho Lee:
  Highly Linear RF CMOS Variable Attenuators With Adaptive Body Biasing. 1023-1033
  
• Jihwan Kim, Youngchang Yoon, Hyungwook Kim, Kyu Hwan An, Woonyun Kim, Hyun-Woong Kim, Chang-Ho Lee, Kevin T. Kornegay:
  A Linear Multi-Mode CMOS Power Amplifier With Discrete Resizing and Concurrent Power Combining Structure. 1034-1048
  
• Jagdish Nayayan Pandey, Brian P. Otis:
  A Sub-100 μ W MICS/ISM Band Transmitter Based on Injection-Locking and Frequency Multiplication. 1049-1058
  
• Arun Natarajan, Scott K. Reynolds, Ming-Da Tsai, Sean T. Nicolson, Jing-Hong Conan Zhan, Dong Gun Kam, Duixian Liu, Yen-Lin Oscar Huang, Alberto Valdes-Garcia, Brian A. Floyd:
  A Fully-Integrated 16-Element Phased-Array Receiver in SiGe BiCMOS for 60-GHz Communications. 1059-1075
  
• Changhui Hu, Rahul Khanna, Jay J. Nejedlo, Kangmin Hu, Huaping Liu, Patrick Yin Chiang:
  A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization. 1076-1088
  
• James Roach, Lee-Wen Chen, Peter Clarke, Amit Dikshit, Francis M. Rotella:
  Key Aspects in Modeling of Thin Epi SOS Technology With Application of BSIMSOI. 1089-1099
  
• Jian Liu, Xin Wang, Hui Zhao, Qiang Fang, Albert Z. Wang, Lin Lin, He Tang, Siqiang Fan, Bin Zhao, Shi-Jie Wen, Richard Wong:
  Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS. 1100-1110
  
• Mohamed El-Nozahi, Ahmed A. Helmy, Edgar Sánchez-Sinencio, Kamran Entesari:
  An Inductor-Less Noise-Cancelling Broadband Low Noise Amplifier With Composite Transistor Pair in 90 nm CMOS Technology. 1111-1122
  
• Joohwa Kim, James F. Buckwalter:
  Staggered Gain for 100+ GHz Broadband Amplifiers. 1123-1136
  
• Christian Knochenhauer, Christoph Scheytt, Frank Ellinger:
  A Compact, Low-Power 40-GBit/s Modulator Driver With 6-V Differential Output Swing in 0.25- μ m SiGe BiCMOS. 1137-1146
  
• Youngmin Park, David D. Wentzloff:
  An All-Digital 12 pJ/Pulse IR-UWB Transmitter Synthesized From a Standard Cell Library. 1147-1157
  
• Shih-Hao Huang, Wei-Zen Chen, Yu-Wei Chang, Yang-Tung Huang:
  A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18- μħbox m CMOS Technology. 1158-1169
  
• Niksa Tadic, Milena Zogovic, Wolfgang Gaberl, Horst Zimmermann:
  A 78.4 dB Photo-Sensitivity Dynamic Range, 285 T Ω Hz Transimpedance Bandwidth Product BiCMOS Optical Sensor for Optical Storage Systems. 1170-1182
  
• Sanquan Song, Vladimir Stojanovic:
  A 6.25 Gb/s Voltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links. 1183-1197
  
• Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang:
  A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique. 1198-1213
  
• Vaibhav Karkare, Sarah Gibson, Dejan Markovic:
  A 130- μ W, 64-Channel Neural Spike-Sorting DSP Chip. 1214-1222
  
• Kris Myny, Monique J. Beenhakkers, Nick A. J. M. van Aerle, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans:
  Unipolar Organic Transistor Circuits Made Robust by Dual-Gate Technology. 1223-1230
  
• Ha Le-Thai, Huy-Hieu Nguyen, Hoai-Nam Nguyen, Hong-Soon Cho, Jeong-Seon Lee, Sang-Gug Lee:
  Correction to "An IF Bandpass Filter Based on a Low Distortion Transconductor" [Dec 10 2634-2646]. 1231
  
• Gerry Taylor, Ian Galton:
  Correction to "A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC" [Nov 10 2250-2261]. 1231
  

Volume 46, Number 6, June 2011

• Hooman Darabi, Henrik Jensen, Alireza Zolfaghari:
  Analysis and Design of Small-Signal Polar Transmitters for Cellular Applications. 1237-1249
  
• Bo-Yu Lin, Shen-Iuan Liu:
  Analysis and Design of D-Band Injection-Locked Frequency Dividers. 1250-1264
  
• Mohammed M. Abdul-Latif, Mohamed M. Elsayed, Edgar Sánchez-Sinencio:
  A Wideband Millimeter-Wave Frequency Synthesis Architecture Using Multi-Order Harmonic-Synthesis and Variable N -Push Frequency Multiplication. 1265-1283
  
• Patrick P. Mercier, Anantha P. Chandrakasan:
  A Supply-Rail-Coupled eTextiles Transceiver for Body-Area Networks. 1284-1295
  
• Farzad Inanlou, Mehdi Kiani, Maysam Ghovanloo:
  A 10.2 Mbps Pulse Harmonic Modulation Based Transceiver for Implantable Medical Devices. 1296-1306
  
• Deping Huang, Wei Li, Jin Zhou, Ning Li, Jinghong Chen:
  A Frequency Synthesizer With Optimally Coupled QVCO and Harmonic-Rejection SSBmixer for Multi-Standard Wireless Receiver. 1307-1320
  
• Sameh A. Ibrahim, Behzad Razavi:
  Low-Power CMOS Equalizer Design for 20-Gb/s Systems. 1321-1336
  
• Masum Hossain, Anthony Chan Carusone:
  7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS. 1337-1348
  
• Lechang Liu, Takayasu Sakurai, Makoto Takamiya:
  A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver. 1349-1359
  
• Masanori Furuta, Mai Nozawa, Tetsuro Itakura:
  A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique. 1360-1370
  
• Yongjian Tang, Joost Briaire, Kostas Doris, Robert van Veldhoven, Pieter C. W. van Beek, Hans Hegt, Arthur H. M. van Roermund:
  A 14 bit 200 MS/s DAC With SFDR > 78 dBc, IM3 < - 83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping. 1371-1381
  
• Mostafa Savadi Oskooei, Nasser Masoumi, Mahmud Kamarei, Henrik Sjöland:
  A CMOS 4.35-mW +22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers. 1382-1391
  
• Chengliang Qian, Jordi Parramon, Edgar Sánchez-Sinencio:
  A Micropower Low-Noise Neural Recording Front-End Circuit for Epileptic Seizure Detection. 1392-1405
  
• Alexander J. Casson, Esther Rodríguez-Villegas:
  A 60 pW g_mC Continuous Wavelet Transform Circuit for Portable EEG Systems. 1406-1415
  
• Bo Xiang, Dan Bao, Shuangqu Huang, Xiaoyang Zeng:
  An 847-955 Mb/s 342-397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 μ m CMOS. 1416-1432
  
• Ming Gu, Shantanu Chakrabartty:
  A 100 pJ/bit, (32, 8) CMOS Analog Low-Density Parity-Check Decoder Based on Margin Propagation. 1433-1442
  
• Juan Antonio Leñero-Bardallo, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
  A 3.6 μ s Latency Asynchronous Frame-Free Event-Driven Dynamic-Vision-Sensor. 1443-1455
  
• Stefano Stanzione, Daniele Puntin, Giuseppe Iannaccone:
  CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability. 1456-1463
  
• Chen Zheng, Dongsheng Ma:
  A 10-MHz Green-Mode Automatic Reconfigurable Switching Converter for DVS-Enabled VLSI Systems. 1464-1477
  
• Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
  1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD. 1478-1487
  
• Kyu-Young Kim, Yonghwan Kim, Doo-Chan Lee, Yu-Ri Kang, Hoon Ki Kim, Soo-Won Kim, Jongsun Park:
  An Energy Efficient V_PP Generator With Fast Ramp-Up Time for Mobile DRAM. 1488-1494
  
• Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, Chris H. Kim:
  A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches. 1495-1505
  

Volume 46, Number 7, July 2011

• Siva V. Thyagarajan, Shanthi Pavan, Prabu Sankar:
  Active-RC Filters Using the Gm-Assisted OTA-RC Technique. 1522-1533
  
• Qinwen Fan, Fabio Sebastiano, Johan H. Huijsing, Kofi A. A. Makinwa:
  A 1.8 μ W 60 nV √ Hz Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes. 1534-1543
  
• Fabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Salvatore Drago, Domine Leenaerts, Bram Nauta:
  A 65-nm CMOS Temperature-Compensated Mobility-Based Frequency Reference for Wireless Sensor Networks. 1544-1552
  
• Joselyn Torres, Adrian Colli-Menchi, Miguel Angel Rojas González, Edgar Sánchez-Sinencio:
  A Low-Power High-PSRR Clock-Free Current-Controlled Class-D Audio Amplifier. 1553-1561
  
• Enrique Prefasi, Susanna Patón, Luis Hernández:
  A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm ² 65 nm CMOS Circuit. 1562-1574
  
• Timmy Sundström, Christer Svensson, Atila Alvandpour:
  A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS. 1575-1584
  
• Pieter Harpe, Cui Zhou, Yu Bi, N. P. van der Meijs, Xiaoyan Wang, Kathleen Philips, Guido Dolmans, Harmke de Groot:
  A 26 μ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios. 1585-1595
  
• Hongtao Xu, Yorgos Palaskas, Ashoke Ravi, Masoud Sajadieh, Mohammed A. El-Tanani, Krishnamurthy Soumyanath:
  A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application. 1596-1605
  
• David Murphy, Qun Jane Gu, Yi-Cheng Wu, Heng-Yu Jian, Zhiwei Xu, Adrian Tang, Frank Wang, Mau-Chung Frank Chang:
  A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver. 1606-1617
  
• Pietro Andreani, Kirill Kozmin, Per Sandrup, Magnus Nilsson, Thomas Mattsson:
  A TX VCO for WCDMA/EDGE in 90 nm RF CMOS. 1618-1626
  
• Nitz Saputra, John R. Long:
  A Fully-Integrated, Short-Range, Low Data Rate FM-UWB Transmitter in 90 nm CMOS. 1627-1635
  
• Silvia Soldà, Michele Caruso, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig, Andrea Neviani:
  A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13 μħbox m CMOS. 1636-1647
  
• Kyoohyun Lim, Sunki Min, Sang-Hoon Lee, Jaewoo Park, Kisub Kang, Hwahyeong Shin, Hyunchul Shim, Sechang Oh, Sungho Kim, Jong-Ryul Lee, Changsik Yoo, Kukjin Chun:
  A 2x2 MIMO Tri-Band Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX/WLAN Applications. 1648-1658
  
• Jonathan Borremans, Gunjan Mandal, Vito Giannini, Björn Debaillie, Mark Ingels, Tomohiro Sano, Bob Verbruggen, Jan Craninckx:
  A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers. 1659-1671
  
• Matteo Perenzoni, Nicola Massari, David Stoppa, Lucio Pancheri, Mattia Malfatti, Lorenzo Gonzo:
  A 160 ˟ 120-Pixels Range Camera With In-Pixel Correlated Double Sampling and Fixed-Pattern Noise Correction. 1672-1681
  
• Lasse Aaltonen, Antti Kalanti, Mika Pulkkinen, Matti Paavola, Mika Kämäräinen, K. A. I. Halonen:
  A 2.2 mA 4.3 mm ² ASIC for a 1000°/s 2-Axis Capacitive Micro-Gyroscope. 1682-1692
  
• Kamran Souri, Kofi A. A. Makinwa:
  A 0.12 mm ² 7.4 μ W Micropower Temperature Sensor With an Inaccuracy of ± 0.2°C (3 Sigma ) From - 30°C to 125°C. 1693-1700
  
• Xiao Liu, Andreas Demosthenous, Nick Donaldson:
  An Integrated Stimulator With DC-Isolation and Fine Current Control for Implanted Nerve Tripoles. 1701-1714
  
• Tom Van Breussegem, Michiel Steyaert:
  Monolithic Capacitive DC-DC Converter With Single Boundary-Multiphase Control and Voltage Domain Stacking in 90 nm CMOS. 1715-1727
  
• Hannes Reinisch, Stefan Gruber, Hartwig Unterassinger, Martin Wiessflecker, Günter Hofer, Wolfgang Pribyl, Gerald Holweg:
  An Electro-Magnetic Energy Harvesting System With 190 nW Idle Mode Power Consumption for a BAW Based Wireless Sensor Node. 1728-1741
  
• Joyce Kwong, Anantha P. Chandrakasan:
  An Energy-Efficient Biomedical Signal Processing Platform. 1742-1753
  
• Christoph Studer, Schekeb Fateh, Dominik Seethaler:
  ASIC Implementation of Soft-Input Soft-Output MIMO Detection Using MMSE Parallel Interference Cancellation. 1754-1765
  

Volume 46, Number 8, August 2011

• Zhiming Deng, Ali M. Niknejad:
  A 4-Port-Inductor-Based VCO Coupling Method for Phase Noise Reduction. 1772-1781
  
• Thomas William Brown, Farhad Farhabakhshian, Ankur Guha Roy, Terri S. Fiez, Kartikeya Mayaram:
  A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency. 1782-1795
  
• Debopriyo Chowdhury, Lu Ye, Elad Alon, Ali M. Niknejad:
  An Efficient Mixed-Signal 2.4-GHz Polar Power Amplifier in 65-nm CMOS Technology. 1796-1809
  
• Sujiang Rong, Howard C. Luong:
  Design and Analysis of Varactor-Less Interpolative-Phase-Tuning Millimeter-Wave LC Oscillators with Multiphase Outputs. 1810-1819
  
• Edward K. F. Lee:
  An Inside Body Power and Bidirectional Data Transfer IC Module Pair. 1820-1831
  
• Anthony Chan Carusone, Hemesh Yasotharan, Tony Shuo-Chun Kao:
  CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors. 1832-1842
  
• Taehyoun Oh, Ramesh Harjani:
  A 6-Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os. 1843-1856
  
• Ranko Sredojevic, Vladimir Stojanovic:
  Fully Digital Transmit Equalizer With Dynamic Impedance Modulation. 1857-1869
  
• Wenjing Yin, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
  A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. 1870-1880
  
• Sang-Hyun Cho, Chang-Kyo Lee, Jong-Kee Kwon, Seung-Tak Ryu:
  A 550- μħbox W 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction. 1881-1892
  
• Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu:
  SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration. 1893-1903
  
• Gokce Keskin, Jonathan Proesel, Jean-Olivier Plouchart, Lawrence T. Pileggi:
  Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs. 1904-1918
  
• Bart De Vuyst, Pieter Rombouts:
  A 5-MHz 11-Bit Self-Oscillating Sigma Delta Modulator With a Delay-Based Phase Shifter in 0.025 mm ². 1919-1927
  
• Mengmeng Du, Hoi Lee, Jin Liu:
  A 5-MHz 91% Peak-Power-Efficiency Buck Regulator With Auto-Selectable Peak- and Valley-Current Control. 1928-1939
  
• Sudhir S. Kudva, Ramesh Harjani:
  Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range. 1940-1951
  

Volume 46, Number 9, September 2011

• ChuanKang Liang, Behzad Razavi:
  Transmitter Linearization by Beamforming. 1956-1969
  
• Pui-In Mak, Rui Paulo Martins:
  A 0.46-mm ² 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS. 1970-1984
  
• Giuseppe Papotto, Francesco Carrara, Giuseppe Palmisano:
  A 90-nm CMOS Threshold-Compensated RF Energy Harvester. 1985-1997
  
• Gaurab Banerjee, Manas Behera, Mohamad A. Zeidan, Rick Chen, Kenneth Barnett:
  Analog/RF Built-in-Self-Test Subsystem for a Mobile Broadcast Video Receiver in 65-nm CMOS. 1998-2008
  
• Martin Jahn, Herbert Knapp, Andreas Stelzer:
  A 122-GHz SiGe-Based Signal-Generation Chip Employing a Fundamental-Wave Oscillator With Capacitive Feedback Frequency-Enhancement. 2009-2020
  
• Narasimha Lanka, Satwik A. Patnaik, Ramesh Harjani:
  Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-mum Technology. 2021-2032
  
• Prabir C. Maulik, Ping Wing Lai:
  Frequency Tuning of Wide Temperature Range CMOS LC VCOs. 2033-2040
  
• Jae-sun Seo, David Blaauw, Dennis Sylvester:
  Crosstalk-Aware PWM-Based On-Chip Links With Self-Calibration in 65 nm CMOS. 2041-2052
  
• Hyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong-June Park:
  A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface. 2053-2063
  
• Ching-Yuan Yang, Jun-Hong Weng, Hsuan-Yu Chang:
  A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35- μ m SiGe BiCMOS. 2064-2072
  
• Seunghyun Lim, Jimin Cheon, Youngcheol Chae, Wunki Jung, Dong-Hun Lee, Minho Kwon, Kwisung Yoo, Seogheon Ham, Gunhee Han:
  A 240-frames/s 2.1-Mpixel CMOS Image Sensor With Column-Shared Cyclic ADCs. 2073-2083
  
• Mohamed M. Elsayed, Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio:
  A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator. 2084-2098
  
• Muhammed Bolatkale, Michiel A. P. Pertijs, Wilko J. Kindt, Johan H. Huijsing, Kofi A. A. Makinwa:
  A Single-Temperature Trimming Technique for MOS-Input Operational Amplifiers Achieving 0.33 μ V/°C Offset Drift. 2099-2107
  
• Pengfei Li, Deepak Bhatia, Lin Xue, Rizwan Bashirullah:
  A 90-240 MHz Hysteretic Controlled DC-DC Buck Converter With Digital Phase Locked Loop Synchronization. 2108-2119
  
• Hanh-Phuc Le, Seth Sanders, Elad Alon:
  Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters. 2120-2131
  
• Wancheng Zhang, Qiuyu Fu, Nan-Jian Wu:
  A Programmable Vision Chip Based on Multiple Levels of Parallel Processors. 2132-2147
  
• Takashi Ohsawa, Kosuke Hatsuda, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoki Higashi:
  Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells. 2148-2157
  
• Elaine Ou, S. Simon Wong:
  Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory. 2158-2170
  
• Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama:
  A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. 2171-2179
  
• Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda, Shinji Miyano, Ken Takeuchi:
  Improvement of Read Margin and Its Distribution by V_TH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection. 2180-2188
  

Volume 46, Number 10, October 2011

• Axel Tessmann, Arnulf Leuther, Volker Hurm, Ingmar Kallfass, Hermann Massler, Michael Kuri, Markus Riessle, Martin Zink, Rainer Lösch, Matthias Seelmann-Eggebert, Matthias Schlechtweg, Oliver Ambacher:
  Metamorphic HEMT MMICs and Modules Operating Between 300 and 500 GHz. 2193-2202
  
• Munkyo Seo, Miguel Urteaga, Jonathan Hacker, Adam Young, Zach Griffith, Vibhor Jain, Richard Pierson, Petra Rowell, Anders Skalare, Alejandro Peralta, Robert Lin, David Pukala, Mark J. W. Rodwell:
  InP HBT IC Technology for Terahertz Frequencies: Fundamental Oscillators Up to 0.57 THz. 2203-2214
  
• Munehiko Nagatani, Hideyuki Nosaka, Shogo Yamanaka, Kimikazu Sano, Koichi Murata:
  Ultrahigh-Speed Low-Power DACs Using InP HBTs for Beyond-100-Gb/s/ch Optical Transmission Systems. 2215-2225
  
• Ricardo Andres Aroca, Peter Schvan, Sorin P. Voinigescu:
  A 2.4- ħbox V _pp 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies. 2226-2239
  
• Leland Gilreath, Vipul Jain, Payam Heydari:
  Design and Analysis of a W-Band SiGe Direct-Detection-Based Passive Imaging Receiver. 2240-2252
  
• Yiping Feng, Gaku Takemura, Shunji Kawaguchi, Nobuyuki Itoh, Peter R. Kinget:
  Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers. 2253-2267
  
• Ajay Balankutty, Peter R. Kinget:
  An Ultra-Low Voltage, Low-Noise, High Linearity 900-MHz Receiver With Digitally Calibrated In-Band Feed-Forward Interferer Cancellation in 65-nm CMOS. 2268-2283
  
• Marco Crepaldi, Chen Li, Jorge R. Fernandes, Peter R. Kinget:
  An Ultra-Wideband Impulse-Radio Transceiver Chipset Using Synchronized-OOK Modulation. 2284-2299
  
• Ching-Che Chung, Chiun-Yao Ko:
  A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology. 2300-2311
  
• Yahya M. Tousi, Ehsan Afshari:
  A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS. 2312-2325
  
• Jinghua Zhang, Yong Lian, Libin Yao, Bo Shi:
  A 0.6-V 82-dB 28.6- μ W Continuous-Time Audio Delta-Sigma Modulator. 2326-2335
  
• Jingxue Lu, Ranjit Gharpurey:
  Design and Analysis of a Self-Oscillating Class D Audio Amplifier Employing a Hysteretic Comparator. 2336-2349
  
• Xiaocheng Jing, Philip K. T. Mok, Ming Chak Lee:
  A Wide-Load-Range Constant-Charge-Auto-Hopping Control Single-Inductor-Dual-Output Boost Regulator With Minimized Cross-Regulation. 2350-2362
  
• Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto:
  A Scalable Massively Parallel Processor for Real-Time Image Processing. 2363-2373
  
• John Keane, Wei Zhang, Chris H. Kim:
  An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization. 2374-2385
  
• Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai:
  Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing. 2386-2395
  
• Dong-Su Lee, Young-Hyun Jun, Bai-Sun Kong:
  Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM. 2396-2405
  
• Shuhei Tanakamaru, Ken Takeuchi:
  A 0.5 V Operation V _TH Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems. 2406-2415
  
• Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene:
  A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy. 2416-2430
  
• Satyanand Nalam, Benton H. Calhoun:
  5T SRAM With Asymmetric Sizing for Improved Read Stability. 2431-2442
  

Volume 46, Number 11, November 2011

• Pieter Harpe, Cui Zhou, Kathleen Philips, Harmke de Groot:
  A 0.8-mW 5-bit 250-MS/s Time-Interleaved Asynchronous Digital Slope ADC. 2450-2457
  
• Omid Rajaee, Seiji Takeuchi, Mitsuru Aniya, Koichi Hamashita, Un-Ku Moon:
  Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer. 2458-2468
  
• Jun-Gi Jo, Jinho Noh, Changsik Yoo:
  A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA. 2469-2477
  
• Payam Lajevardi, Anantha P. Chandrakasan, Hae-Seung Lee:
  Zero-Crossing Detector Based Reconfigurable Analog System. 2478-2487
  
• Yu-Huei Lee, Tzu-Chi Huang, Yao-Yi Yang, Wen-Shen Chou, Ke-Horng Chen, Chen-Chih Huang, Ying-Hsi Lin:
  Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter. 2488-2499
  
• Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
  A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. 2500-2513
  
• Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, Chen-Yi Lee:
  A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters. 2514-2523
  
• Ji-Hoon Park, Brian C. Richards, Borivoje Nikolic:
  A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band. 2524-2534
  
• Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, K. Yanagisawa:
  A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. 2535-2544
  
• Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe:
  A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. 2545-2551
  
• Yasuhiro Take, Noriyuki Miura, Tadahiro Kuroda:
  A 30 Gb/s/Link 2.2 Tb/s/mm ² Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface. 2552-2559
  
• Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong:
  250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. 2560-2570
  
• Chen-Yen Ho, Wei-Shan Chan, Yung-Yu Lin, Tsung-Hsien Lin:
  A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver. 2571-2582
  
• Hsi-Han Chiang, Fu-Chien Huang, Chao-Shiun Wang, Chorng-Kuang Wang:
  A 90 nm CMOS V-Band Low-Noise Active Balun With Broadband Phase-Correction Technique. 2583-2591
  
• Yi-Chun Shih, Tueng Shen, Brian P. Otis:
  A 2.3 μ W Wireless Intraocular Pressure/Temperature Monitor. 2592-2601
  
• Ruonan Han, Yaming Zhang, Dominique Coquillat, Hadley Videlier, Wojciech Knap, Elliott Brown, Kenneth K. O:
  A 280-GHz Schottky Diode Detector in 130-nm Digital CMOS. 2602-2612
  
• Anuj Madan, Michael J. McPartlin, Zhan-Feng Zhou, Chun-Wen Paul Huang, Christophe Masse, John D. Cressler:
  Fully Integrated Switch-LNA Front-End IC Design in CMOS: A Systematic Approach for WLAN. 2613-2622
  
• Prakash E. Thoppay, Catherine Dehollain, Michael M. Green, Michel J. Declercq:
  A 0.24-nJ/bit Super-Regenerative Pulsed UWB Receiver in 0.18- μ m CMOS. 2623-2634
  
• Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa:
  A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications. 2635-2649
  
• Koji Takinami, Richard Strandberg, Paul C. P. Liang, Gregoìre Le Grand de Mercey, Tony Wong, Mahnaz Hassibi:
  A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter. 2650-2660
  
• Wenbo Liu, Pingli Huang, Yun Chiu:
  A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration. 2661-2672
  
• Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis:
  A Digitally Corrected 5-mW 2-MS/s SC Delta Sigma ADC in 0.25- μ m CMOS With 94-dB SFDR. 2673-2684
  
• Chenling Huang, Pikul Sarkar, Shantanu Chakrabartty:
  Rail-to-Rail, Linear Hot-Electron Injection Programming of Floating-Gate Voltage Bias Generators at 13-Bit Resolution. 2685-2692
  
• Guang Ge, Cheng Zhang, Gian Hoogzaad, Kofi A. A. Makinwa:
  A Single-Trim CMOS Bandgap Reference With a 3Sigma Inaccuracy of ± 0.15% From - 40°C to 125°C. 2693-2701
  
• Seng Oon Toh, Zheng Guo, Tsu-Jae King Liu, Borivoje Nikolic:
  Characterization of Dynamic SRAM Stability in 45 nm CMOS. 2702-2712
  
• Adam Teman, Lidor Pergament, Omer Cohen, Alexander Fish:
  A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM). 2713-2726
  

Volume 46, Number 12, 2011

• Jafar Savoj, Yiannos Manoli, Hooman Darabi, Yorgos Palaskas, Michael Moyal:
  Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. 2739-2744
  
• Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
  A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs_rms Integrated Jitter at 4.5-mW Power. 2745-2758
  
• Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu:
  A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration. 2759-2771
  
• Sachin Rao, Qadeer Khan, Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Pavan Kumar Hanumolu:
  A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique. 2772-2783
  
• Mykhaylo A. Teplechuk, Anthony Gribben, Christophe Amadi:
  True Filterless Class-D Audio Amplifier. 2784-2793
  
• Rong Wu, Johan H. Huijsing, Kofi A. A. Makinwa:
  A Current-Feedback Instrumentation Amplifier With a Gain Error Reduction Loop and 0.06% Untrimmed Gain Error. 2794-2806
  
• Saurav Bandyopadhyay, Yogesh K. Ramadass, Anantha P. Chandrakasan:
  20 µ A to 100 mA DC-DC Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45 nm CMOS. 2807-2820
  
• Kostas Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard Van der Weide:
  A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS. 2821-2833
  
• Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult:
  An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS. 2834-2844
  
• Wei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu:
  A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With >70 dB SFDR up to 500 MHz. 2845-2856
  
• Muhammed Bolatkale, Lucien J. Breems, Robert Rutten, Kofi A. A. Makinwa:
  A 4 GHz Continuous-Time ΔΣ ADC With 70 dB DR and -74 dBFS THD in 125 MHz BW. 2857-2868
  
• John G. Kauffman, Pascal Witte, Joachim Becker, Maurits Ortmanns:
  An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR. 2869-2881
  
• Nima Maghari, Un-Ku Moon:
  A Third-Order DT ΔΣ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer. 2882-2891
  
• Lars Risbo, Rahmi Hezar, Burak Kelleci, Halil Kiper, Mounir Fares:
  Digital Approaches to ISI-Mitigation in High-Resolution Oversampled Multi-Level D/A Converters. 2892-2903
  
• Robert Bogdan Staszewski, Khurram Waheed, Fikret Dulger, Oren Eliezer:
  Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS. 2904-2919
  
• Ahmad Mirzaei, Hooman Darabi, David Murphy:
  A Low-Power Process-Scalable Super-Heterodyne Receiver With Integrated High-Q Filters. 2920-2932
  
• Michiel C. M. Soer, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet:
  Spatial Interferer Rejection in a Four-Element Beamforming Receiver Front-End With a Switched-Capacitor Vector Modulator. 2933-2942
  
• Ugo Decanis, Andrea Ghilioni, Enrico Monaco, Andrea Mazzanti, Francesco Svelto:
  A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves. 2943-2955
  
• Kuo-Ken Huang, David D. Wentzloff:
  A 60 GHz Antenna-Referenced Frequency-Locked Loop in 0.13 µ CMOS for Wireless Sensor Networks. 2956-2965
  
• Omeed Momeni, Ehsan Afshari:
  A Broadband mm-Wave and Terahertz Traveling-Wave Frequency Multiplier on CMOS. 2966-2976
  
• Sang-Min Yoo, Jeffrey S. Walling, Eum Chan Woo, Benjamin Jann, David J. Allstot:
  A Switched-Capacitor RF Power Amplifier. 2977-2987
  
• Kenichi Okada, Ning Li, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Shogo Ito, Win Chaivipas, Ryo Minami, Tatsuya Yamaguchi, Yasuaki Takeuchi, Hiroyuki Yamagishi, Makoto Noda, Akira Matsuzawa:
  A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c. 2988-3004
  
• Alexandre Siligaris, Olivier Richard, Baudouin Martineau, Christopher Mounet, Fabrice Chaix, Romain Ferragut, Cedric Dehos, Jérôme Lanteri, Laurent Dussopt, Silas D. Yamamoto, Romain Pilard, Pierre Busson, Andreia Cathelin, Didier Belot, Pierre Vincent:
  A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications. 3005-3017
  
• Maryam Tabesh, Jiashu Chen, Cristian Marcu, Lingkai Kong, Shinwon Kang, Ali M. Niknejad, Elad Alon:
  A 65 nm CMOS 4-Element Sub-34 mW/Element 60 GHz Phased-Array Transceiver. 3018-3032
  
• Shih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee:
  W-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology. 3033-3046
  
• Chi-yao Yu, Ivan Siu-Chuang Lu, Yen-horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, Hsiang-Hui Chang, Wen-Chang Lee, Sheng-Jui Huang, Tzung-Han Wu, Chinq-Shiun Chiu, George Chien:
  A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC. 3047-3060
  
• Michael Youssef, Alireza Zolfaghari, Behnam Mohammadi, Hooman Darabi, Asad A. Abidi:
  A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS. 3061-3074
  
• Hannes Reinisch, Martin Wiessflecker, Stefan Gruber, Hartwig Unterassinger, Günter Hofer, Michael Klamminger, Wolfgang Pribyl, Gerald Holweg:
  A Multifrequency Passive Sensing Tag With On-Chip Temperature Sensor and Off-Chip Sensor Interface Using EPC HF and UHF RFID Technology. 3075-3088
  
• Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz:
  11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications. 3089-3100
  
• Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura:
  A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. 3101-3112
  
• Satoshi Fukuda, Yasufumi Hino, Sho Ohashi, Takahiro Takeda, Hiroyuki Yamagishi, Satoru Shinke, Kenji Komori, Masahiro Uno, Yoshiyuki Akiyama, Kenichi Kawasaki, Ali Hajimiri:
  A 12.5+12.5 Gb/s Full-Duplex Plastic Waveguide Interconnect. 3113-3125
  
• Freeman Zhong, Shaolei Quan, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang:
  A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS. 3126-3139
  
• Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune:
  An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS. 3140-3149
  
• Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu:
  A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. 3150-3162
  
• Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu:
  A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery. 3163-3173
  

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