Parallel Processing Letters, Volume 18, 2008

Volume 18, Number 1, March 2008

• Peter Krusche:
  Experimental Evaluation of BSP Programming Libraries. 7-21
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• Clemens Grelck, Steffen Kuthe, Sven-Bodo Scholz:
  A Hybrid Shared Memory Execution Model for a Data Parallel Language with I/O. 23-37
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• Frédéric Gava:
  A Modular Implementation of Data Structures in Bulk-Synchronous Parallel ML. 39-53
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• Emmanuel Chailloux, Vivien Ravet, Julien Verlaguet:
  Hirondml: Fair Threads Migrations for Objective Caml. 55-69
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• Noemi de La Rocque Rodriguez, Silvana Rossetto:
  Integrating Remote Invocations with Asynchronism and Cooperative Multitasking. 71-85
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• Gagarine Yaikhom:
  Message Passing without Memory Copy. 87-100
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• Jost Berthold, Rita Loogen:
  The Impact of Dynamic Channels on Functional Topology Skeletons. 101-115
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• Michael Poldner, Herbert Kuchen:
  On Implementing the Farm Skeleton. 117-131
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• Ignacio Peláez, Francisco Almeida, Daniel González:
  High Level Parallel Skeletons for Dynamic Programming. 133-147
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• Roberto Di Cosmo, Zheng Li, Susanna Pelagatti, Pierre Weis:
  Skeletal Parallel Programming with OCamlP3l 2.0. 149-164
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• Sonia Campa:
  Evaluating Computational Costs while Handling Data and Control Parallelism. 165-174
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• Marco Aldinucci, Anne Benoit:
  Automatic Mapping of Assist Applications Using Process Algebra. 175-188
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• Wayne Goddard, Stephen T. Hedetniemi, David Pokrass Jacobs, Pradip K. Srimani, Zhenyu Xu:
  Self-Stabilizing Graph Protocols. 189-199
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Volume 18, Number 2, June 2008

• Jan Lemeire, Erik F. Dirkx, Walter Colitti:
  Modeling the Performance of Communication Schemes on Network Topologies. 205-220
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• Clemens Grelck, Sven-Bodo Scholz, Alexander V. Shafarenko:
  A Gentle Introduction to S-Net: Typed Stream Processing and Declarative Coordination of Asynchronous Components. 221-237
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• Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungsook Yang, Nader Bagherzadeh:
  On Design and Application Mapping of a Network-on-Chip(NoC) Architecture. 239-255
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• Chris R. Jesshope:
  Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips. 257-274
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• Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle:
  Adaptive Communication Architectures for Runtime Reconfigurable System-on-Chips. 275-289
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• Konstantinos Tatas, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Stephan Wong:
  Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d²-CMP) Using FPGAs. 291-306
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• F. Furman Haddix:
  An Order Degree alternator for Arbitrary Topologies. 307-322
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