ACM Transactions on Architecture and Code Optimization (TACO), Volume 1

Volume 1, Number 1, March 2004

• Brad Calder, Dean M. Tullsen:
  Introduction. 1-2
  
• Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
  Reducing instruction cache energy consumption using a compiler-based strategy. 3-33
  
• Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong, Isaac L. Chuang, Mark Oskin:
  Datapath and control for quantum wires. 34-61
  
• Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore:
  TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. 62-93
  
• Kevin Skadron, Mircea R. Stan, Karthik Sankaranarayanan, Wei Huang, Sivakumar Velusamy, David Tarjan:
  Temperature-aware microarchitecture: Modeling and implementation. 94-125
  

Volume 1, Number 2, June 2004

• Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli:
  Removing communications in clustered microarchitectures through instruction replication. 127-151
  
• Yu Bai, R. Iris Bahar:
  A low-power in-order/out-of-order issue queue. 152-179
  
• Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Phil Diodato, Stefanos Kaxiras:
  Implementing branch-predictor decay using quasi-static memory cells. 180-219
  
• Oliverio J. Santana, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero:
  A low-complexity fetch architecture for high-performance superscalar processors. 220-245
  

Volume 1, Number 3, September 2004

• Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan:
  A compiler framework for speculative optimizations. 247-271
  
• Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn:
  Interaction cost and shotgun profiling. 272-304
  
• Karthik Sankaranarayanan, Kevin Skadron:
  Profile-based adaptation for cache decay. 305-322
  
• Fen Xie, Margaret Martonosi, Sharad Malik:
  Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling. 323-367
  

Volume 1, Number 4, December 2004

• Allan Hartstein, Thomas R. Puzak:
  The optimum pipeline depth considering both power and performance. 369-388
  
• Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez:
  Toward kilo-instruction processors. 389-417
  
• Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan:
  An analysis of a resource efficient checkpoint architecture. 418-444
  
• Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee:
  Tolerating memory latency through push prefetching for pointer-intensive applications. 445-475