Volume 42,
Number 1,
January 1993
Cache Memory
Communication Protocols
Hypercube Fault Tolerance
- Shahram Latifi:
Combinatorial Analysis of the Fault-Diameter of the n-cube.
27-33
Interleaved Memories
- Gurindar S. Sohi:
High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study.
34-44
Microcode Design
Multicomputer Dependability
Parallel Processor Architecture
Server Policies
Correspondence
- Yu Hen Hu, S. Naganathan:
An Angle Recoding Method for CORDIC Algorithm Implementation.
99-102
- David M. Mandelbaum:
Some Results on a SRT Type Division Scheme.
102-106
- Tai-Haur Kuo, Hung Chang Lin, Robert C. Potter, Dave Schupe:
Multiple-Valued Counter.
106-109
- T. Aaron Gulliver, Vijay K. Bhargava:
A Systematic (16, 8) Code for Correcting Double Errors and Detecting Triple-Adjacent Errors.
109-112 ,
Comment:
IEEE Trans. Computers 43(1): 125(1994)
- Andrew Spray, Simon Jones:
Performance Tradeoffs in Rings of Data-Driven Elements.
113-118
- Christophe Mazenc, Xavier Merrheim, Jean-Michel Muller:
Computing Functions cos^{-1} and sin^{-1} Using Cordic.
118-122
- Hwa C. Torng, Martin Day:
Interrupt Handling for Out-of-Order Execution Processors.
122-127
Volume 42,
Number 2,
February 1993
- Sreejit Chakravarty:
A Characterization of Binary Decision Diagrams.
129-137 ,
Comments:
IEEE Trans. Computers 43(3): 383-384(1994)
- Imrich Chlamtac, Aura Ganz, Martin G. Kienzle:
An HIPPI Interconnection System.
138-150
- Biswanath Mukherjee, Subrata Banerjee:
Alternative Strategies for Improving the Fairness in and an Analytical Model of the DQDB Network.
151-167
- Jean Duprat, Jean-Michel Muller:
The CORDIC Algorithm: New Results for Fast VLSI Implementation.
168-178
- Niraj K. Jha:
Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers.
179-189
- Andrew Choi, Manfred Ruschitzka:
Managing Locality Sets: The Model and Fixed-Size Buffers.
190-204
- Douglas M. Blough, Andrzej Pelc:
Diagnosis and Repair in Multiprocessor Systems.
205-217
- K. T. Sun, H. C. Fu:
A Hybrid Neural Network Model for Solving Optimization Problems.
218-227
- Tiko Kameda, Slawomir Pilarski, André Ivanov:
Notes on Multiple Input Signature Analysis.
228-234
Correspondence
Volume 42,
Number 3,
March 1993
- Andreas Farid Pour, Mark D. Hill:
Performance Implications of Tolerating Cache Faults.
257-267
- Antonio Lioy:
On the Equivalence of Fanout-Point Faults.
268-271
- Nageswara S. V. Rao:
Expected-Value Analysis of Two Single Fault Diagnosis Algorithms.
272-280
- Jordan L. Holt, Jenq-Neng Hwang:
Finite Precision Error Analysis of Neural Network Hardware Implementations.
281-290
- Ananth Sankar, Richard J. Mammone:
Growing and Pruning Neural Tree Networks.
291-299
- Martin Lades, Jan C. Vorbrüggen, Joachim M. Buhmann, Jörg Lange, Christoph von der Malsburg, Rolf P. Würtz, Wolfgang Konen:
Distortion Invariant Object Recognition in the Dynamic Link Architecture.
300-311
- Krishna R. Pattipati, Yong Li, Henk A. P. Blom:
A Unified Framework for the Performability Evaluation of Fault-Tolerant Computer Systems.
312-326
- Meera Balakrishnan, C. S. Raghavendra:
An Analysis of a Reliability Model for Repairable Fault-Tolerant Systems.
327-339
- Aloke K. Das, Parimal Pal Chaudhuri:
Vector Space Theoretic Analysis of Additive Cellular Automata and Its Application for Pseudoexhaustive Test Pattern Generation.
340-352
Correspondence
Volume 42,
Number 4,
April 1993
- Theodora A. Varvarigou, Vwani P. Roychowdhury, Thomas Kailath:
A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models.
385-395
- Chris H. Perleberg, Alan Jay Smith:
Branch Target Buffer Design and Optimization.
396-412
- Marcel Lapointe, Huu Tue Huynh, Paul Fortier:
Systematic Design of Pipelined Recursive Filters.
413-426
- Elio D. Di Claudio, Gianni Orlandi, Francesco Piazza:
A Systolic Redundant Residue Arithmetic Error Correction Circuit.
427-432
- G. Robert Redinbo, Leonard M. Napolitano Jr., David D. Andaleon:
Multibit Correcting Data Interface for Fault-Tolerant Systems.
433-446
- Nageswara S. V. Rao:
Computational Complexity Issues in Operative Diagnosis of Graph-Based Systems.
447-457
- Ashwini K. Nanda, Laxmi N. Bhuyan:
Design and Analysis of Cache Coherent Multistage Interconnection Networks.
458-470
- Ram Raghavan, John P. Hayes:
Reducing Inerference Among Vector Accesses in Interleaved Memories.
471-483
- Shambhu J. Upadhyaya, Hoang Pham:
Analysis of Noncoherent Systems and an Architecture for the Computation of the System Reliability.
484-493
Correspondence
Volume 42,
Number 5,
May 1993
- Simon Y. Berkovich:
An Overlaying Technique for Solving Linear Equations in Real-Time Computing.
513-517
- Douglas M. Blough, Andrzej Pelc:
A Clustered Failure Model for the Memory Array Reconfiguration Problem.
518-528
- Jesse Zhixi Fang, Mi Lu:
An Iteration Partition Approach for Cache or Local Memory Thrashing on Parallel Processing.
529-546
- Yuichi Saitoh, Hideki Imai:
Some Codes for Correcting and Detecting Unidirectional Byte Errors.
547-552
- Hirotsugu Kakugawa, Satoshi Fujita, Masafumi Yamashita, Tadashi Ae:
Availability of k-Coterie.
553-558 ,
Comments:
IEEE Trans. Computers 43(12): 1457(1994)
- Barry G. Douglass:
Rearrangeable Three-Stage Interconnection Networks and Their Routing Properties.
559-567
- Daniel Brand, Tsutomu Sasao:
Minimization of AND-EXOR Expressions Using Rewrite Rules.
568-576
- Chunming Qiao, Rami G. Melhem:
Time-Division Optical Communications in Multiprocessor Arrays.
577-590
- Pablo P. Trabado, Antonio Lloris-Ruíz, Julio Ortega:
Solution of Switching Equations Based on a Tabular Algebra.
591-596 ,
Additions:
IEEE Trans. Computers 43(3): 365-367(1994)
- Andrew Lim, Siu-Wing Cheng, Sartaj Sahni:
Optimal Joining of Compacted Cells.
597-607
Correspondence
- Giovanni Dimauro, Sebastiano Impedovo, Giuseppe Pirlo:
A New Technique for Fast Number Comparison in the Residue Number System.
608-61
- Ding-Zhu Du, Yuh-Dauh Lyuu, D. Frank Hsu:
Line Digraph Iterations and Connectivity Analysis of de Bruijn and Kautz Graphs.
612-616 ,
Corrigendum:
IEEE Transactions on Computers 45(7):
863 (1996)
- David T. Harper III, Yashodara Costa:
Analytical Estimation of Vector Access Performance in Parallel Memory Architectures.
616-624
- Seshu V. R. Madabhushi, S. Lakshmivarahan, Sudarshan K. Dhall:
A Note on Orthogonal Graphs.
624-630
- Daniel J. Rosenkrantz, S. S. Ravi:
Improved Bounds for Algorithm-Based Fault Tolerance.
630-635
- Tao Wang, Xinhua Zhuang, Xiaoliang Xing, Xipeng Xiao:
A Neuron-Weighted Learning Algorithm and Its Hardware Implementation in Associative Memories.
636-640
Volume 42,
Number 6,
June 1993
- Janusz Rajski, Jerzy Tyszer:
Accumulator-Based Compaction of Test Responses.
643-650
- Edward K. Lee, Randy H. Katz:
The Performance of Parity Placements in Disk Arrays.
651-664
- Nabanita Das, Bhargab B. Bhattacharya, Jayasree Dattagupta:
Isomorphism of Conflict Graphs in Multistage Interconnection Networks and Its Application to Optimal Routing.
665-677
- Russ Miller, Viktor K. Prasanna, Dionisios I. Reisis, Quentin F. Stout:
Parallel Computations on Reconfigurable Meshes.
678-692
- Stephen E. Eldridge, Colin D. Walter:
Hardware Implementation of Montgomery's Modular Multiplication Algorithm.
693-699
- Stanislaw J. Piestrak:
The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks.
700-712
- Yung-Yuan Chen, Shambhu J. Upadhyaya:
Reliability, Reconfiguration, and Spare Allocation Issues in Binary-Tree Architectures Based on Multiple-Level Redundancy.
713-723
- Israel Koren, Zahava Koren, Charles H. Stapper:
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits.
724-734
Correspondence
Volume 42,
Number 7,
July 1993
Cordic Arithmetic
Error Detection
Fault-Tolerant Systems
Heterogeneous Distributed Systems
Number Systems
Pipeline Processing
Residue Number Systems
- Hari Krishna, Jenn-Dong Sun:
On Theory and Fast Algorithms for Error Correction in Residue Number System Product Codes.
840-853
Systolic Arrays
Vector Processing
- Woei Lin:
Manipulating General Vectors on Synchronous Binary N-Cube.
863-871
Yield Modeling
Correspondence
Volume 42,
Number 8,
August 1993
Concurrent Testing
Dependability Evaluation
Fault-Tolerance
Interconnection Networks
Multiple-Valued Logic
Residue Number Systems
Test-Pattern Generation
Correspondence
- Judy Stephens, Vijaj Raghavan:
On Single-Fault Set Diagnosability in the PMC Model.
981-983
- Anindya Das, Krishnaiyan Thulasiraman, Vinod K. Agarwal, K. B. Lakshmanan:
Multiprocessor Fault Diagnosis Under Local Constraints.
984-988
- Sung-Kwong Park, Jung H. Kim:
Geometrical Learning Algorithm for Multilayer Neural Networks in a Binary Field.
988-992
- Dinesh P. Mehta, Sartaj Sahni:
A Data Structure for Circular String Analysis and Visualization.
992-997
- John E. Sasinowski, Jay K. Strosnider:
A Dynamic Programming Algorithm for Cache/Memory Partitioning for Real-Time Systems.
997-1001
- Khaled Day, Anand R. Tripathi:
Embedding of Cycles in Arrangement Graphs.
1002-1006
- Steven Arno, Ferrell S. Wheeler:
Signed Digit Representations of Minimal Hamming Weight.
1007-1009
- Hannes Brunner, Andreas Curiger, Max Hofstetter:
On Computing Multiplicative Inverses in GF(2^m).
1010-1015
- Sarit Mukherjee, Satish K. Tripathi, Dipak Ghosal:
A Multiclass Priority-Based Slotted-Ring LAN and Its Analysis.
1015-1020
- T. R. N. Rao, Gui Liang Feng, Mahadev S. Kolluru, Jien-Chung Lo:
Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning.
1020-1024 ,
Correction:
IEEE Transactions on Computers 43(5):
640 (1994)
Volume 42,
Number 9,
September 1993
Asynchronous State Assignment
- P. David Fisher, Sheng-Fu Wu:
Race-Free State Assignment for Synthesizing Large-Scale Asynchronous Sequential Logic Circuits.
1025-1034
Built-In Test
Cache Design
Eigenvalue Computation
Fault Detection
Fault-Tolerant Hypercubes
Fault-Tolerant Meshes
Interconnection Networks
Scan Testing
Correspondence
Volume 42,
Number 10,
October 1993
Cache Design
Carry-Select Adders
- Akhilesh Tyagi:
A Reduced-Area Scheme for Carry-Select Adders.
1163-1170
Computational Models
Failure Repair Models
Fault Tolerance
Neural Networks
Nonrestoring Division
Correspondence
Volume 42,
Number 11,
November 1993
Array Configuration
Error-Correcting Codes
- Mao Chao Lin:
Constant Weight Codes for Correcting Symmetric Errors and Detecting Unidirectional Errors.
1294-1302
Fault Tolerance
Logic Minimization
Network Modeling
Sequential Testing
Signature Monitoring
- Kent D. Wilken:
An Optimal Graph-Construction Approach to Placing Program Signatures for Signature Monitoring.
1372-1381
Wafer Packing
Correspondence
Volume 42,
Number 12,
December 1993
Cache Design
- Qing Yang:
Introducing a New Cache Design into Vector Computers.
1411-1424
Database Management Systems
Dependability Evaluation
Dram Design
- Pinaki Mazumder:
Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit.
1453-1468
Interconnection Networks
- Ching Yuh Jan, A. Yavuz Oruç:
Fast Self-Routing Permutation Switching on an Asymptotically Minimum Cost Network.
1469-1479 ,
Corrections:
IEEE Transactions on Computers 43(9):
1120 (1994)
- Robert A. Rowley, Bella Bose:
Fault-Tolerant Ring Embedding in de Bruijn Networks.
1480-1486
Synchronizer Reliability
Correspondence
Copyright © Sat Nov 21 01:36:57 2009
by Michael Ley (ley@uni-trier.de)
