Volume 45,
Number 1,
January 1996
Cellular Automata
Error Correction and Detection
Logic Design
Privacy and Security
Testing and Design for Testability
Brief Contributions
Volume 45,
Number 2,
February 1996
Fault Tolerance
Interconnection Network Topology
Routing and Broadcasting Algorithms
Theory and Algorithms
Brief Contributions
Volume 45,
Number 3,
March 1996
Built-In Self-Test
Compiler Techniques
- Meng-chou Chang, Feipei Lai:
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme.
278-293
Subject Area
Memory Management
Brief Contributions
Correction to Previous Paper
Volume 45,
Number 4,
April 1996
Algorithm-Based Fault Tolerance and Result-Checking
Consensus and Agreement
Concurrent Error Detection
Brief Contributions
- Spyros Tragoudas:
Min-Cut Partitioning on Underlying Tree and Graph Structures.
470-474
- Nader Bagherzadeh, Martin Dowd, Nayla Nassif:
Embedding an Arbitrary Binary Tree into the Star Graph.
475-481
- Jovan Dj. Golic, Slobodan V. Petrovic:
Correlation Attacks on Clock-Controlled Shift Registers in Keystream Generators.
482-486
- Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri:
Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach.
487-490
- Hédi Nabli, Bruno Sericola:
Performability Analysis: A New Algorithm.
491-494
- C. S. Raghavendra, M. A. Sridhar:
Global Commutative and Associative Reduction Operations in Faulty SIMD Hypercubes.
495-498
- V. S. S. Nair, Jacob A. Abraham, Prithviraj Banerjee:
Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes.
499-503
- Nitin H. Vaidya:
Comparison of Duplex and Triplex Memory Reliability.
503-507
- Sihai Xiao, Xiaofa Shih, Guilang Feng, T. R. N. Rao:
A Generalization of the Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems.
508-511
Corrections
Volume 45,
Number 5,
May 1996
Generalized Spectral Analysis
- Michael J. Corinthios:
A Weighted Z Spectrum, Parallel Algorithm, and Processors for Mathematical Model Estimation.
513-528
Interconnection Networks
Memory and Memory Mangement
Modeling and Performance Evaluation
Processor Architecture
Brief Contributions
Comments
Volume 45,
Number 6,
June 1996
Fault Tolerant Communication
Routing Algorithms and Switching Schemes
Task Assignment
Brief Contributions
Comments
Volume 45,
Number 7,
July 1996
Cellular Automata
Processor Design
Real-Time Scheduling
Theory and Algorithms
Brief Contributions
- Christof Paar:
A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields.
856-861
Comments
- Bin Wei:
Comments on ``A Multiaccess Frame Buffer Architecture''.
862
Volume 45,
Number 8,
August 1996
Fault Tolerance
Testing Algorithms,
Methods and Tools
Brief Contributions
Volume 45,
Number 9,
September 1996
Complexity Theory
Encoding and Decoding
Logic Design
Brief Contributions
- Ming Zhang, Stamatis Vassiliadis, José G. Delgado-Frias:
Sigmoid Generators for Neural Computing Using Piecewise Approximations.
1045-1049
- Luigi Ciminiera, Paolo Montuschi:
Carry-Save Multiplication Schemes without Final Addition.
1050-1055
- Zhen Liu, Ting-Yi Sung:
Routing and Transmitting Problems in de Bruijn Networks.
1056-1062
- Stamatis Vassiliadis, Sorin Cotofana, Koen Bertels:
2-1 Additions and Related Arithmetic Operations with Threshold Logic.
1062-1067
- Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata:
Unified Mixed Radix 2-4 Redundant CORDIC Processor.
1068-1073
- Charles U. Martel, W. Melody Moh, Teng-Sheng Moh:
Dynamic Prioritized Conflict Resolution on Multiple Access Broadcast Networks.
1074-1079
- Chung-Len Lee, Meng-Lieh Sheu:
A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines.
1079-1083
- Haomin Wu, Marek A. Perkowski, Xiaoqiang Zheng, Nan Zhuang:
Generalized Partially-Mixed-Polarity Reed-Muller Expansionand Its Fast Computation.
1084-1088
Volume 45,
Number 10,
October 1996
Computer Architecture
Diagnosis and Testing
Memory and Memory Menagement
Brief Contributions
Volume 45,
Number 11,
November 1996
Fault Tolerance
- Hagbae Kim, Kang G. Shin:
Design and Analysis of an Optimal Instruction-Retry Policy for TMR Controller Computers.
1217-1225
- Francisco V. Brasileiro, Paul D. Ezhilchelvan, Santosh K. Shrivastava, Neil A. Speirs, Sha Tao:
Implementing Fail-Silent Nodes for Distributed Systems.
1226-1238
- Amber Roy-Chowdhury, Prithviraj Banerjee:
Algorithm-Based Fault Location and Recovery for Matrix Computations on Multiprocessor Systems.
1239-1247
- Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi:
A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults.
1248-1256
Parallel Computation
Routing and Switching Schemes
Brief Contributions
- Rolf Drechsler, Michael Theobald, Bernd Becker:
Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions.
1294-1299
- Winfrid G. Schneeweiss:
A Necessary and Sufficient Criterion for the Monotonicity of Boolean Functions with Deterministic and Stochastic.
1300-1302
- Nian-Feng Tzeng, Guanghua Lin:
Efficient Determination of Maximum Incomplete Subcubes in Hypercubes with Faults.
1303-1308
- Jacqueline Walker, Antonio Cantoni:
A New Synchronizer Design.
1308-1311
- Yuan-Chieh Hsu, Sandeep K. Gupta:
A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits.
1312-1318
- Knuth Stener Grimsrud, James K. Archibald, Richard L. Frost, Brent E. Nelson:
Locality as a Visualization Tool.
1319-1326
- Satoshi Fujita, Masafumi Yamashita:
Fast Gossiping on Mesh-Bus Computers.
1326-1330
- Hagbae Kim, Kang G. Shin:
Sequencing Tasks to Minimize the Effects of Near-Coincident Faults in TMR Controller Computers.
1331-1337
- Nirmal R. Saxena, Edward J. McCluskey:
Counting Two-State Transition-Tour Sequences.
1337-1342
Volume 45,
Number 12,
December 1996
Computer Arithmetic
Testing
Brief Contributions
Copyright © Tue Nov 24 20:52:35 2009
by Michael Ley (ley@uni-trier.de)
