IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 11

Volume 11, Number 1, January 1992

• Tracy Larrabee:
  Test pattern generation using Boolean satisfiability. 4-15
  
• Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal:
  Using an asymmetric error model to study aliasing in signature analysis registers. 16-25
  
• Hans-Joachim Wunderlich, Sybille Hellebrand:
  The pseudoexhaustive test of sequential circuits. 26-33
  
• Thomas M. Sarfert, Remo G. Markgraf, Michael H. Schulz, Erwin Trischler:
  A hierarchical test pattern generation system based on high-level primitives. 34-44
  
• John D. Calhoun, Franc Brglez:
  A framework and method for hierarchical test generation. 45-67
  
• W. David Ballew, Lauren M. Streb:
  Board-level boundary scan: regaining observability with an additional IC. 68-75
  
• David L. Landis:
  A test methodology for wafer scale system. 76-82
  
• Paul H. Bardell:
  Calculating the effects of linear dependencies in m-sequences used as test stimuli. 83-86
  
• Srinivas Devadas, Kurt Keutzer:
  Synthesis of robust delay-fault-testable circuits: theory. 87-101
  
• Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu:
  Layout placement for sliced architecture. 102-114
  
• Chung-Kuan Cheng, David N. Deutsch, Craig Shohara, Mark Taparauskas, Mark Bubien:
  Geometric compaction on channel routing. 115-127
  
• Gerd Nanz, Peter Dickinger, Siegfried Selberherr:
  Calculation of contact currents in device simulation. 128-136
  

Volume 11, Number 2, February 1992

• Bo-Gwan Kim, Donald L. Dietmeyer:
  Multilevel logic synthesis with extended arrays. 142-157
  
• David W. Knapp, Marianne Winslett:
  A prescriptive formal model for data-path hardware. 158-184
  
• Kuochen Wang, Sy-Yen Kuo:
  Computer-aided modeling and evaluation of reconfigurable VLSI processor arrays with VHDL. 185-197
  
• Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel:
  PROOFS: a fast, memory-efficient sequential circuit fault simulator. 198-207
  
• Mary L. Bailey:
  How circuit size affects parallelism. 208-215
  
• Uminder Singh, C. Y. Roger Chen:
  From logic to symbolic layout for gate matrix. 216-227
  
• Takayasu Sakurai, Bill Lin, A. Richard Newton:
  Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction. 228-234
  
• Yusuf Leblebici, Sung-Mo Kang:
  Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation. 235-246
  
• Irith Pomeranz, Zvi Kohavi:
  A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion. 247-259
  
• Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham:
  Test compaction for sequential circuits. 260-267
  
• Xiaoyu Song:
  An algorithm for L-shaped channel routing in a diagonal model. 267-270
  

Volume 11, Number 3, March 1992

• Srinivas Devadas, Kurt Keutzer:
  Synthesis of robust delay-fault-testable circuits: practice. 277-300
  
• Bernhard Eschermann, Hans-Joachim Wunderlich:
  Optimized synthesis techniques for testable sequential circuits. 301-312
  
• Gary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison:
  On properties of algebraic transformations and the synthesis of multifault-irredundant circuits. 313-321
  
• Karem A. Sakallah, Trevor N. Mudge, Oyekunle A. Olukotun:
  Analysis and design of latch-controlled synchronous digital circuits. 322-333
  
• Bixia Li, Deren Gu:
  SSCNAP: a program for symbolic analysis of switched capacitor circuits. 334-340
  
• Tak K. Tang, Michel S. Nakhla:
  Analysis of high-speed VLSI interconnects using the asymptotic waveform evaluation technique. 341-352
  
• Bradly J. Cooke, John L. Prince, Andreas C. Cangellaris:
  S-parameter analysis of multiconductor, integrated circuit interconnect systems. 353-360
  
• Maria C. Bernardo, Robert J. Buck, Lihsin Liu, William A. Nazaret, Jerome Sacks, William J. Welch:
  Integrated circuit design optimization using a sequential strategy. 361-372
  
• Srinivas Devadas, Kurt Keutzer, Jacob K. White:
  Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. 373-383
  
• Michel Dagenais, Serge Gaiotti, Nicholas C. Rumin:
  Transistor-level estimation of worst-case delays in MOS VLSI circuits. 384-395
  
• Bruno Baccus, Dominique Collard, Emmanuel Dubois:
  Adaptive mesh refinement for multilayer process simulation using the finite element method. 396-403
  
• Miron Abramovici, David T. Miller, Rabindra K. Roy:
  Dynamic redundancy identification in automatic test generation. 404-407
  
• Hyung K. Lee, Dong S. Ha:
  Comments on `A method of fault simulation based on stem regions'. 407-408
  

Volume 11, Number 4, April 1992

• Stefaan Note, Francky Catthoor, Gert Goossens, Hugo De Man:
  Combined hardware selection and pipelining in high-performance data-path design. 413-423
  
• Thomas F. Hayes, John J. Barrett:
  Modeling of multiconductor systems for packaging and interconnecting high-speed digital IC's. 424-431
  
• Eugene Z. Xia, Resve A. Saleh:
  Parallel waveform-Newton algorithms for circuit simulation. 432-442
  
• Eduard Cerny, John P. Hayes, Nicholas C. Rumin:
  Accuracy of magnitude-class calculations in switch-level modeling. 443-452
  
• Allen C.-H. Wu, Daniel D. Gajski:
  Partitioning algorithms for layout synthesis from register-transfer netlists. 453-463
  
• Nobuo Funabiki, Yoshiyasu Takefuji:
  A parallel algorithm for channel routing problems [VLSI]. 464-474
  
• Chung-Kuan Cheng, Ximtie Deng, Yuh-Zen Liao, So-Zen Yao:
  Symbolic layout compaction under conditional design rules. 475-486
  
• Walter B. Richardson, Graham F. Carey, Brian J. Mulvaney:
  Modeling phosphorus diffusion in three dimensions. 487-496
  
• Zeyi Wang, Qiming Wu:
  A two-dimensional resistance simulator using the boundary element method. 497-504
  
• Keith R. Green, Jerry G. Fossum:
  A pragmatic approach to integrated process/device/circuit simulation for IC technology development. 505-512
  
• George L. Matthaei, Gilbert C. Chinn, Charles H. Plott, Nadir Dagli:
  A simplified means for computation for interconnect distributed capacitances and inductances. 513-524
  
• Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao, Michael Nicolaidis:
  An SFS Berger check prediction ALU and its application to self-checking processor designs. 525-540
  

Volume 11, Number 5, May 1992

• TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
  Efficiently computing communication complexity for multilevel logic synthesis. 545-554
  
• David M. Lewis:
  A compiled-code hardware accelerator for circuit simulation. 555-565
  
• Luis Miguel Silveira, Jacob K. White, Horácio C. Neto, Luís M. Vidigal:
  On exponential fitting for circuit simulation. 566-574
  
• Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen:
  M³-a multilevel mixed-mode mixed A/D simulator. 575-585
  
• John Y. Lee, Xiaoli Huang, Ronald A. Rohrer:
  Pole and zero sensitivity calculation in asymptotic waveform evaluation. 586-597
  
• Donald J. Erdman, Donald J. Rose:
  Newton waveform relaxation techniques for tightly coupled systems. 598-606
  
• John F. Beetem:
  Hierarchical topological sorting of apparent loops via partitioning. 607-619
  
• Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic:
  A detailed router for field-programmable gate arrays. 620-628
  
• John R. F. McMacken, Savvas G. Chamberlain:
  A numerical model for two-dimensional transient simulation of amorphous silicon thin-film transistors. 629-637
  
• José Pineda de Gyvez, Chennian Di:
  IC defect sensitivity for footprint-type spot defects. 638-658
  
• Kuen-Jong Lee, Melvin A. Breuer:
  Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults. 659-670
  
• Deodatta R. Apte, Mark E. Law:
  Comparison of iterative methods for AC analysis in PISCES-IIB. 671-673
  

Volume 11, Number 6, June 1992

• David W. Knapp:
  Fasolt: a program for feedback-driven data-path optimization. 677-695
  
• David C. Ku, Giovanni De Micheli:
  Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits. 696-718
  
• Yung-Ho Shih, Sung-Mo Kang:
  Analytic transient solution of general MOS circuit primitives. 719-731
  
• Terence B. Hook:
  Automatic extraction of circuit models from layout artwork for a BiCMOS technology. 732-738
  
• Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong:
  Provably good performance-driven global routing. 739-752
  
• Charles R. Bonapace, Chi-Yuan Lo:
  An O(n log m) algorithm for VLSI design rule checking. 753-758
  
• Joohyun Jin, Jerry G. Fossum:
  Non-quasi-static modeling/implementation of BJT current crowding for seminumerical mixed-mode device/circuit simulation. 759-767
  
• André Ivanov, Yervant Zorian:
  Count-based BIST compaction schemes and aliasing probability computation. 768-777
  
• Janusz Rajski, Jagadeesh Vasudevamurthy:
  The testability-preserving concurrent decomposition and factorization of Boolean expressions. 778-793
  
• Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò:
  Testability measures in pseudorandom testing. 794-800
  
• Michael J. Bryan, Srinivas Devadas, Kurt Keutzer:
  Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks. 800-803
  

Volume 11, Number 7, July 1992

• Tom Dhaene, Daniel De Zutter:
  Selection of lumped element models for coupled lossy transmission lines. 805-815
  
• Mary L. Bailey:
  A time-based model for investigating parallel logic-level simulation. 816-824
  
• Sharad Malik, Luciano Lavagno, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Symbolic minimization of multilevel logic and the input encoding problem. 825-843
  
• Sung-Soo Kim, Chong-Min Kyung:
  Circuit placement on arbitrarily shaped regions using the self-organization principle. 844-854
  
• Stephan Müller, Kevin Kells, Wolfgang Fichtner:
  Automatic rectangle-based adaptive mesh generation without obtuse angles. 855-863
  
• Kenneth M. McDonald, Joseph G. Peters:
  Smallest paths in simple rectilinear polygons. 864-875
  
• Hans-Rudolf Heeb, Wolfgang Fichtner:
  A module generator based on the PQ-tree algorithm. 876-884
  
• Scott W. Hadley, Brian L. Mark, Anthony Vannelli:
  An efficient eigenvector approach for finding netlist partitions. 885-892
  
• Andrew B. Kahng, Gabriel Robins:
  A new class of iterative Steiner tree heuristics with good performance. 893-902
  
• Shankar Pennathur, Harry H. L. Kwok:
  Simulation of charge transfer in GaAs Cermet-Gate CCDs. 903-910
  
• Edward W. Scheckler, Alexander S. Wong, Robert K. Wang, Goodwin R. Chin, John R. Camagna, Andrew R. Neureuther, Robert W. Dutton:
  A utility-based integrated system for process simulation. 911-920
  
• Hiroyoshi Tanimoto, Naoyuki Shigyo:
  Discretization error in MOSFET device simulation. 921-925
  
• Eun Sei Park, M. Ray Mercer:
  An efficient delay test generation system for combinational logic circuits. 926-938
  

Volume 11, Number 8, August 1992

• Maciej J. Ciesielski, Seiyang Yang:
  PLADE: a two-stage PLA decomposition. 943-954
  
• Rajiv Jain, Alice C. Parker, Nohbyung Park:
  Predicting system-level area and delay for pipelined and nonpipelined designs. 955-965
  
• Albert V. Ferris-Prabhu:
  On the assumptions contained in semiconductor yield models. 966-975
  
• Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng:
  An H-V alternating router. 976-991
  
• Ting-Chi Wang, Martin D. F. Wong:
  Optimal floorplan area optimization. 992-1002
  
• Kartikeya Mayaram, Donald O. Pederson:
  Coupling algorithms for mixed-level circuit and device simulation. 1003-1012
  
• Mamoru Kurata, Shin Nakamura:
  An explicit method of numerical integration for the complete set of semiconductor device equations. 1013-1023
  
• Yeong-Yil Yang, Chong-Min Kyung:
  HALO: an efficient global placement strategy for standard cells. 1024-1031
  
• J. Richard Griffith, Michel S. Nakhla:
  Mixed frequency/time domain analysis of nonlinear circuits. 1032-1043
  
• Somchai Prasitjutrakul, William J. Kubitz:
  A performance-driven global router for custom VLSI chip design. 1044-1051
  

Volume 11, Number 9, September 1992

• Fur-Shing Tsai, Yu-Chin Hsu:
  STAR: An automatic data path allocator. 1053-1064
  
• Kwang-Ting Cheng, Jing-Yang Jou:
  A functional fault model for sequential machines. 1065-1073
  
• Lars W. Hagen, Andrew B. Kahng:
  New spectral methods for ratio cut partitioning and clustering. 1074-1085
  
• Xiaodong Zhang:
  Dynamic and static load balancing for solving block bordered circuit equations on multiprocessors. 1086-1094
  
• Majid Sarrafzadeh, Chak-Kuen Wong:
  Hierarchical Steiner tree construction in uniform orientations. 1095-1103
  
• Tsuneo Okubo, Takashi Watanabe, Kou Wada, Kazuyuki Saito:
  A novel geometric resizing technique for data conversion from CAD data to electron beam exposure data. 1104-1113
  
• Masayoshi Shirahata, Hiromi Kusano, Norihiko Kotani, Shigeru Kusanoki, Yoichi Akasaka:
  A mobility model including the screening effect in MOS inversion layer. 1114-1119
  
• Peter M. Maurer:
  Two new techniques for unit-delay compiled simulation. 1120-1130
  
• Larry G. Jones:
  An incremental zero/integer delay switch-level simulation environment. 1131-1139
  
• Mark Hirsch, Daniel P. Siewiorek:
  The effect of placement of automatically extracted structure. 1140-1152
  
• Weiping Shi, W. Kent Fuchs:
  Probabilistic analysis and algorithms for reconfiguration of memory arrays. 1153-1160
  
• Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu:
  Optimal diagnostic methods for wiring interconnects. 1161-1166
  
• Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
  Heuristic minimization of Boolean relations using testing techniques. 1166-1172
  

Volume 11, Number 10, October 1992

• Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell:
  Topological channel routing [VLSI]. 1177-1197
  
• Kevin S. Eshbaugh:
  Generation of correlated parameters for statistical circuit simulation. 1198-1206
  
• Bogdan J. Falkowski, Ingo Schäfer, Marek A. Perkowski:
  Effective computer methods for the calculation of Rademacher-Walsh spectrum for completely and incompletely specified Boolean functions. 1207-1226
  
• Mark William Kahrs:
  Silicon compilation of very high level language. 1227-1246
  
• Hong June Park, Ping Keung Ko, Chenming Hu:
  A non-quasi-static MOSFET model for SPICE-AC analysis. 1247-1257
  
• Rui Wang, Omar Wing:
  Transient analysis of dispersive VLSI interconnects terminated in nonlinear loads. 1258-1277
  
• Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski:
  BIST of PCB interconnects using boundary-scan architecture. 1278-1288
  
• Sy-Yen Kuo, Ing-Yi Chen:
  Efficient reconfiguration algorithms for degradable VLSI/WSI arrays. 1289-1300
  
• Slawomir Pilarski, Andrzej Krasniewski, Tiko Kameda:
  Estimating testing effectiveness of the circular self-test path technique. 1301-1316
  
• Uwe Hinsberger, Reiner Kolla:
  A cell-based approach to performance optimization of fanout-free circuits. 1317-1322
  

Volume 11, Number 11, November 1992

• Thang Nguyen Bui, Willie Hsu, SingLing Lee:
  A 2.5 approximation algorithm for the multi-via assignment problem. 1325-1333
  
• Ze-Yi Wang, Ke-Chih Wu, Robert W. Dutton:
  An approach to construct pre-conditioning matrices for block iteration of linear equations. 1334-1343
  
• Carlos H. Díaz, Sung-Mo Kang:
  New algorithms for circuit simulation of device breakdown. 1344-1354
  
• Gerard A. Allan, Anthony J. Walton, Robert J. Holwill:
  A yield improvement technique for IC layout using local design rules. 1355-1362
  
• Tom Chanak, Rakesh Chadha, Kishore Singhal:
  Switched-capacitor simulation models for full-chips verification. 1363-1371
  
• Colin Gordon, Thomas Blazeck, Raj Mittra:
  Time-domain simulation of multiconductor transmission lines with frequency-dependent losses. 1372-1387
  
• Cheryl Harkness, Daniel P. Lopresti:
  Interval methods for modeling uncertainty in RC timing analysis. 1388-1401
  
• J. Paul Harvey, Mohamed I. Elmasry, Bosco Leung:
  STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits. 1402-1417
  
• James A. Power, W. A. Lane:
  An enhanced SPICE MOSFET model suitable for analog applications. 1418-1425
  
• Peter Vanbekbergen, Gert Goossens, Francky Catthoor, Hugo De Man:
  Optimized synthesis of asynchronous control circuits from graph-theoretic specifications. 1426-1438
  
• Vijay S. Iyengar, Gopalakrishnan Vijayan:
  Optimized test application timing for AC test. 1439-1449
  
• Michel Renovell, Gaston Cambon:
  Electrical analysis and modeling of floating-gate fault. 1450-1458
  
• Michele Favalli, Piero Olivo, Bruno Riccò:
  A probabilistic fault model for `analog' faults in digital CMOS circuits. 1459-1462
  
• Andrew B. Kahng, Gabriel Robins:
  On the performance bounds for a class of rectilinear Steiner tree heuristics in arbitrary dimension. 1462-1465
  

Volume 11, Number 12, December 1992

• Carl Pixley:
  A theory and implementation of sequential hardware equivalence. 1469-1478
  
• Richard W. Thaik, Ngee Lek, Sung-Mo Kang:
  A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays. 1479-1494
  
• Jin-fuw Lee, Chak-Kuen Wong:
  A performance-aimed cell compactor with automatic jogs. 1495-1507
  
• Shan-Ping Chin, Ching-Yuan Wu:
  A new methodology for two-dimensional numerical simulation of semiconductor devices. 1508-1521
  
• H.-C. Chow, W.-S. Feng, James B. Kuo:
  An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation. 1522-1528
  
• Shiu-Kai Chin:
  Verified functions for generating signed-binary arithmetic hardware. 1529-1558
  
• Srinivas Devadas, Kurt Keutzer:
  Validatable nonrobust delay-fault testable circuits via logic synthesis. 1559-1573
  
• Raja Venkateswaran, Pinaki Mazumder, K. G. Shin:
  Restructuring WSI hexagonal processor arrays. 1574-1585
  

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