IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 18

Volume 18, Number 1, January 1999

• Gaetano Borriello, Diederik Verkest, Francky Catthoor:
  Guest Editorial. 1-2
  
• Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
  Local memory exploration and optimization in embedded systems. 3-13
  
• Uwe Eckhardt, Renate Merker:
  Hierarchical algorithm partitioning at system level for an improved utilization of memory structures. 14-24
  
• Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid:
  On the efficiency of formal synthesis-experimental results. 25-32
  
• Henning Dierks:
  Synthesizing controllers from real-time specifications. 33-43
  
• Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess:
  Constraint analysis for DSP code generation. 44-57
  
• Robert Pasko, Patrick Schaumont, Veerle Derudder, Serge Vernalde, Daniela Durackova:
  A new algorithm for elimination of common subexpressions. 58-68
  
• Frank Vahid:
  Techniques for minimizing and balancing I/O during functional partitioning. 69-75
  

Volume 18, Number 2, February 1999

• Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler:
  BDD minimization using symmetries. 81-100
  
• Kenneth Y. Yun, David L. Dill:
  Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations). 101-117
  
• Kenneth Y. Yun, David L. Dill:
  Automatic synthesis of extended burst-mode circuits. II. (Automaticsynthesis). 118-132
  
• Zhaojun Bai, Rodney D. Slone, William T. Smith, Qiang Ye:
  Error bound for reduced system model by Pade approximation via the Lanczos process. 133-141
  
• Toshiyuki Hama, Hiroaki Etoh:
  Topological routing path search algorithm with incremental routability test. 142-150
  
• Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly:
  A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. 151-162
  
• Jin-Tai Yan:
  An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing. 163-171
  
• Edoardo Charbon, Ranjit Gharpurey, Robert G. Meyer, Alberto L. Sangiovanni-Vincentelli:
  Substrate optimization based on semi-analytical techniques. 172-190
  
• Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante:
  SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. 191-202
  
• Yuejian Wu, Saman Adham:
  Scan-based BIST fault diagnosis. 203-211
  
• Atul Garg, Y. L. Le Coz, Hans J. Greub, R. B. Iverson, Robert F. Philhower, Pete M. Campbell, Cliff A. Maier, Sam A. Steidl, Matthew W. Ernest, Russell P. Kraft, Steven R. Carlough, J. W. Perry, Thomas W. Krawczyk Jr., John F. McDonald:
  Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy. 212-219
  
• Dimitrios Kagaris, Spyros Tragoudas:
  On the design of optimal counter-based schemes for test set embedding. 219-230
  
• How-Rern Lin, TingTing Hwang:
  On determining sensitization criterion in an iterative gate sizing process. 231-238
  
• Dhiraj K. Pradhan, Mitrajit Chatterjee:
  GLFSR-a new test pattern generator for built-in-self-test. 238-247
  
• Armen H. Zemanian, Victor A. Chang:
  Exterior templates for capacitance computations [interconnections]. 248-251
  

Volume 18, Number 3, March 1999

• Joseph A. Fernando, Jack S. N. Jean:
  Processor array design with FPGA area constraint. 253-264
  
• Ganesh Lakshminarayana, Niraj K. Jha:
  High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. 265-281
  
• Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska:
  Logic synthesis for engineering change. 282-292
  
• Mustafa Celik, Lawrence T. Pileggi:
  Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees. 293-300
  
• Edoardo Charbon, Paolo Miliozzi, Luca P. Carloni, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli:
  Modeling digital substrate noise injection in mixed-signal IC's. 301-310
  
• Michael W. Beattie, Lawrence T. Pileggi:
  Error bounds for capacitance extraction via window techniques. 311-321
  
• John Lillis, Chung-Kuan Cheng:
  Timing optimization for multisource nets: characterization andoptimal repeater insertion. 322-331
  
• Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska:
  Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits. 332-345
  
• Brian Chess, Tracy Larrabee:
  Creating small fault dictionaries [logic circuit fault diagnosis]. 346-356
  
• Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
  Hierarchical test generation and design for testability methods for ASPPs and ASIPs. 357-370
  

Volume 18, Number 4, April 1999

• Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley:
  Device-level early floorplanning algorithms for RF circuits. 375-388
  
• Kia Bazargan, Samjung Kim, Majid Sarrafzadeh:
  Nostradamus: a floorplanner of uncertain designs. 389-397
  
• Chris C. N. Chu, Martin D. F. Wong:
  Greedy wire-sizing is linear time. 398-405
  
• Jason Cong, Lei He:
  Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. 406-420
  
• Shantanu Dutt, Hasan Arslan, Halim Theny:
  Partitioning using second-order information and stochastic-gainfunctions. 421-435
  
• Huibo Hou, Jiang Hu, Sachin S. Sapatnekar:
  Non-Hanan routing. 436-444
  
• Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky:
  Filling algorithms and analyses for layout density control. 445-462
  
• Evanthia Papadopoulou, D. T. Lee:
  Critical area computation via Voronoi diagrams. 463-474
  
• Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin:
  A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. 475-483
  
• Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng:
  Sequence-pair approach for rectilinear module placement. 484-493
  
• Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas:
  An algorithm for determining repetitive patterns in very large IC layouts. 494-501
  

Volume 18, Number 5, May 1999

• Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha:
  Wavesched: a novel scheduling technique for control-flow intensive designs. 505-523
  
• Miodrag Potkonjak, Jan M. Rabaey:
  Algorithm selection: a quantitative optimization-intensive approach. 524-532
  
• Sven Wuytack, Julio Leao da Silva Jr., Francky Catthoor, Gjalt G. de Jong, Chantal Ykman-Couvreur:
  Memory management for embedded network applications. 533-544
  
• Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
  Improving the efficiency of BDD-based operators by means of partitioning. 545-556
  
• Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioannis Tsoukalas:
  A modeling technique for CMOS gates. 557-575
  
• J. Joseph Clement, Stefan P. Riege, Radenko Cvijetic, Carl V. Thompson:
  Methodology for electromigration critical threshold design rule evaluation. 576-581
  
• Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti:
  Parametric yield formulation of MOS IC's affected by mismatch effect. 582-596
  
• Joao Paulo Costa, Mike Chou, Luis Miguel Silveira:
  Efficient techniques for accurate modeling and simulation ofsubstrate coupling in mixed-signal IC's. 597-607
  
• Chin-Chih Chang, Jason Cong:
  An efficient approach to multilayer layer assignment with anapplication to via minimization. 608-620
  
• Srimat T. Chakradhar, Sujit Dey:
  Resynthesis and retiming for optimum partial scan. 621-630
  
• Laurence Goodby, Alex Orailoglu:
  Redundancy and testability in digital filter datapaths. 631-644
  
• David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah:
  Timing verification of sequential dynamic circuits. 645-658
  
• Young-Jun Cha, Chong S. Rim, Kazuo Nakajima:
  SEGRA: a very fast general area router for multichip modules. 659-665
  
• Irith Pomeranz, Sudhakar M. Reddy:
  A comment on "Improving a nonenumerative method to estimate path delay fault coverage". 665-666
  

Volume 18, Number 6, June 1999

• Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar:
  Primitive delay faults: identification, testing, and design for testability. 669-684
  
• Ben Mathew, Daniel G. Saab:
  Combining multiple DFT schemes with test generation. 685-696
  
• Mahadevamurty Nemani, Farid N. Najm:
  High-level area and power estimation for VLSI circuits. 697-713
  
• Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy:
  Models and algorithms for bounds on leakage in CMOS circuits. 714-725
  
• Catherine H. Gebotys:
  A minimum-cost circulation approach to DSP address-code generation. 726-741
  
• Alain Girault, Bilung Lee, Edward A. Lee:
  Hierarchical finite state machines with multiple concurrency models. 742-760
  
• Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey:
  An output encoding problem and a solution technique. 761-768
  
• Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng:
  POSET timing and its application to the synthesis and verification of gate-level timed circuits. 769-786
  
• Chris C. N. Chu, Martin D. F. Wong:
  A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. 787-798
  
• Hirendu Vaishnav, Massoud Pedram:
  Delay-optimal clustering targeting low-power VLSI circuits. 799-812
  
• Luca Benini, Alessandro Bogliolo, Giuseppe A. Paleologo, Giovanni De Micheli:
  Policy optimization for dynamic power management. 813-833
  
• Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki:
  Synthesis of software programs for embedded control applications. 834-849
  
• Sanghyeon Baeg, William A. Rogers:
  A cost-effective design for testability: clock line control and test generation using selective clocking. 850-861
  
• Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik:
  Using configurable computing to accelerate Boolean satisfiability. 861-868
  

Volume 18, Number 7, July 1999

• Aiguo Xie, Peter A. Beerel:
  Accelerating Markovian analysis of asynchronous systems using state compression. 869-888
  
• Arun N. Lokanathan, Jay B. Brockman:
  A methodology for concurrent process-circuit optimization. 889-902
  
• Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen:
  Equivalence checking of combinational circuits using Boolean expression diagrams. 903-917
  
• Manish Pandey, Randal E. Bryant:
  Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation. 918-935
  
• Sheetanshu L. Pandey, Kothanda Umamageswaran, Philip A. Wilsey:
  VHDL semantics and validating transformations. 936-955
  
• Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou, Michel Langevin, Otmane Aït Mohamed:
  Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs. 956-972
  
• Radu Marculescu, Diana Marculescu, Massoud Pedram:
  Sequence compaction for power estimation: theory and practice. 973-993
  
• Youxin Gao, Martin D. F. Wong:
  Optimal shape function for a bidirectional wire under Elmore delay model. 994-999
  
• Christoph Maier, Markus Emmenegger, Stefano Taschini, Henry Baltes, Jan G. Korvink:
  Equivalent circuit model of resistive IC sensors derived with the box integration method. 1000-1013
  
• Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong:
  Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. 1014-1025
  
• Giri Devarayanadurg, Mani Soma, Prashant Goteti, Sam D. Huynh:
  Test set selection for structural faults in analog IC's. 1026-1039
  
• Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo:
  Static test compaction for synchronous sequential circuits based on vector restoration. 1040-1049
  
• Spyros Tragoudas, Dimitrios Karayiannis:
  A fast nonenumerative automatic test pattern generator for pathdelay faults. 1050-1057
  

Volume 18, Number 8, August 1999

• Supratik Chakraborty, Kenneth Y. Yun, David L. Dill:
  Timing analysis of asynchronous systems using time separation of events. 1061-1076
  
• Peter Voigt Knudsen, Jan Madsen:
  Integrating communication protocol selection with hardware/software codesign. 1077-1095
  
• Shih-Chieh Chang, David Ihsin Cheng:
  Efficient Boolean division and substitution using redundancy addition and removing. 1096-1106
  
• Scott Hauck, Zhiyuan Li, Eric J. Schwabe:
  Configuration compression for the Xilinx XC6200 FPGA. 1107-1113
  
• Anand Raghunathan, Sujit Dey, Niraj K. Jha:
  Register transfer level power optimization with emphasis on glitch analysis and reduction. 1114-1131
  
• Kenneth L. Shepard, Vinod Narayanan, Ron Rose:
  Harmony: static noise analysis of deep submicron digital integrated circuits. 1132-1150
  
• Moshe Meyassed, Robert H. Klenke, James H. Aylor:
  Resolving unknown inputs in mixed-level simulation with sequential elements. 1151-1164
  
• Yoshihiro Yamagami, Yoshifumi Nishio, Akio Ushida, Masayuki Takahashi, Kimihiro Ogawa:
  Analysis of communication circuits based on multidimensional Fourier transformation. 1165-1177
  
• Rajesh Pendurkar, Craig A. Tovey, Abhijit Chatterjee:
  Single-probe traversal optimization for testing of MCM substrate interconnections. 1178-1191
  
• Qian-Yu Tang, Xiaoyu Song, Yuke Wang:
  Diagnosis of clustered faults for identical degree topologies. 1192-1201
  
• Nur A. Touba, Edward J. McCluskey:
  RP-SYN: synthesis of random pattern testable circuits with test point insertion. 1202-1213
  
• Abbas Seifi, Kumaraswamy Ponnambalam, Jiri Vlach:
  Probabilistic design of integrated circuits with correlated input parameters. 1214-1219
  

Volume 18, Number 9, September 1999

• Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev:
  Decomposition and technology mapping of speed-independent circuits using Boolean relations. 1221-1236
  
• Morgan Enos, Scott Hauck, Majid Sarrafzadeh:
  Evaluation and optimization of replication algorithms for logic bipartitioning. 1237-1248
  
• Naresh Maheshwari, Sachin S. Sapatnekar:
  Optimizing large multiphase level-clocked circuits. 1249-1264
  
• Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky:
  On wirelength estimations for row-based placement. 1265-1278
  
• Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta:
  Extraction of functional regularity in datapath circuits. 1279-1296
  
• Chris C. N. Chu, Martin D. F. Wong:
  An efficient and optimal algorithm for simultaneous buffer and wire sizing. 1297-1304
  
• Amir H. Salek, Jinan Lou, Massoud Pedram:
  An integrated logical and physical design flow for deep submicron circuits. 1305-1315
  
• Darko Kirovski, Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith:
  Application-driven synthesis of memory-intensive systems-on-chip. 1316-1326
  
• Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie:
  Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. 1327-1340
  
• Shi-Yu Huang, Kwang-Ting Cheng:
  ErrorTracer: design error diagnosis based on fault simulation techniques. 1341-1352
  
• Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich:
  Analog testing by characteristic observation inference. 1353-1368
  
• Massimo Alioto, Gaetano Palumbo:
  Highly accurate and simple models for CML and ECL gates. 1369-1375
  
• Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
  AutoFix: a hybrid tool for automatic logic rectification. 1376-1384
  
• Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang:
  Slicing floorplans with boundary constraints. 1385-1389
  
• Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan:
  Multilevel spectral hypergraph partitioning with arbitrary vertex sizes. 1389-1399
  
• K. C. Chang:
  Comment on "Event suppression by optimizing VHDL programs". 1400-1401
  

Volume 18, Number 10, October 1999

• Yanbing Li, Wayne Wolf:
  Hardware/software co-synthesis with memory hierarchies. 1405-1417
  
• Wei-Chun Chou, Peter A. Beerel, Kenneth Y. Yun:
  Average-case technology mapping of asynchronous burst-mode circuits. 1418-1434
  
• Hoan H. Pham, Arokia Nathan:
  An integral equation of the second kind for computation of capacitance. 1435-1441
  
• Le-Chin Eugene Liu, Carl Sechen:
  Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic. 1442-1451
  
• Le-Chin Eugene Liu, Carl Sechen:
  Multilayer pin assignment for macro cell circuits. 1452-1461
  
• Hsiao-Ping Tseng, Carl Sechen:
  A gridless multilayer router for standard cell circuits using CTMcells. 1462-1479
  
• Gerard A. Allan, Anthony J. Walton:
  Efficient extra material critical area algorithms. 1480-1486
  
• Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai:
  Fault emulation: A new methodology for fault grading. 1487-1495
  
• Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi:
  Controller-based power management for control-flow intensive designs. 1496-1508
  
• Mahesh B. Patil:
  Extension of the VR discretization scheme for velocity saturation. 1508-1511
  
• Massoud Pedram, Bryan Preas:
  Interconnection analysis for standard cell layouts. 1512-1519
  
• Jin-Tai Yan:
  An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. 1519-1526
  
• Robert P. Dick, Niraj K. Jha:
  Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems". 1527-1527
  

Volume 18, Number 11, November 1999

• Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra:
  Improving the observability and controllability of datapaths foremulation-based debugging. 1529-1541
  
• Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
  An efficient filter-based approach for combinational verification. 1542-1557
  
• Asen Asenov, Andrew R. Brown, John H. Davies, Subhash Saini:
  Hierarchical approach to "atomistic" 3-D MOSFET simulation. 1558-1565
  
• Mario Netzel, Bernd Heinemann, Maik Brett, Dagmar Schipanski:
  Methods for generating and editing merged isotropic/anisotropic triangular-element meshes. 1566-1576
  
• Ganesh Lakshminarayana, Niraj K. Jha:
  FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. 1577-1594
  
• Jason Cong, Chang Wu:
  Optimal FPGA mapping and retiming with efficient initial state computation. 1595-1607
  
• David L. Harris, Mark Horowitz, Dean Liu:
  Timing analysis including clock skew. 1608-1618
  
• Jorge M. Pena, Arlindo L. Oliveira:
  A new algorithm for exact reduction of incompletely specified finite state machines. 1619-1632
  
• Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
  Buffer insertion for noise and delay optimization. 1633-1645
  
• Toshiyuki Hama, Hiroaki Etoh:
  Curvilinear detailed routing with simultaneous wire-spreading and wire-fattening. 1646-1653
  
• Hany L. Abdel-Malek, Abdel-Karim S. O. Hassan, Mohamed H. Heaba:
  A boundary gradient search technique and its applications in design centering. 1654-1660
  
• Indradeep Ghosh, Niraj K. Jha, Sujit Dey:
  A low overhead design for testability and test generation technique for core-based systems-on-a-chip. 1661-1676
  
• Von-Kyoung Kim, Tom Chen:
  On comparing functional fault coverage and defect coverage for memory testing. 1676-1683
  
• Hai Zhou, Martin D. F. Wong:
  Global routing with crosstalk constraints. 1683-1688
  

Volume 18, Number 12, December 1999

• Haris Lekatsas, Wayne Wolf:
  SAMC: a code compression algorithm for embedded processors. 1689-1701
  
• Inki Hong, Darko Kirovski, Gang Qu, Miodrag Potkonjak, Mani B. Srivastava:
  Power optimization of variable-voltage core-based systems. 1702-1714
  
• Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
  High-level synthesis of low-power control-flow intensive circuits. 1715-1729
  
• Alfredo J. Piazza, Can E. Korman, Amro M. Jaradeh:
  A physics-based semiconductor noise model suitable for efficient numerical implementation. 1730-1740
  
• Wolfgang Pyka, Peter Fleischmann, Bernhard Haindl, Siegfried Selberherr:
  Three-dimensional simulation of HPCVD-linking continuum transport and reaction kinetics with topography simulation. 1741-1749
  
• Alexandre Linhares, Horacio Hideki Yanasse, José Ricardo de Almeida Torreao:
  Linear gate assignment: a fast statistical mechanics approach. 1750-1758
  
• Youxin Gao, Martin D. F. Wong:
  Wire-sizing optimization with inductance consideration using transmission-line model. 1759-1767
  
• Haluk Konuk:
  Voltage- and current-based fault simulation for interconnect open defects. 1768-1779
  
• Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth:
  A synthesis for testability scheme for finite state machines using clock control. 1780-1792
  
• Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang:
  Broadcasting test patterns to multiple circuits. 1793-1802
  
• Andreas G. Veneris, Ibrahim N. Hajj:
  Design error diagnosis and correction via test vector simulation. 1803-1816
  
• Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang:
  Crosstalk in VLSI interconnections. 1817-1824
  

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