Volume 20, Number 1, January 2001
Volume 20, Number 2, February 2001
Volume 20, Number 3, March 2001
: Guest editor's introduction to special section on high-level design validation and test.
, Sujit Dey
: Software-based self-testing methodology for processor cores.
, Masahiro Fujita
: Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams.
Volume 20, Number 4, April 2001
Volume 20, Number 5, May 2001
: Global routing by new approximation algorithms for multicommodityflow.
, Rob A. Rutenbar
: Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution.
Volume 20, Number 6, June 2001
Volume 20, Number 7, July 2001
C.-J. Richard Shi
, Sheldon X.-D. Tan
: Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design.
, Kuen-Jong Lee
: Reduction of power consumption in scan-based circuits during testapplication by an input control technique.
Volume 20, Number 8, August 2001
, Wonyong Sung
: Combined word-length optimization and high-level synthesis ofdigital signal processing systems.
, Qinru Qiu
, Massoud Pedram
: Estimation of peak power dissipation in VLSI circuits using thelimiting distributions of extreme order statistics.
, Yen-Tai Lai
: Graph-theory-based simplex algorithm for VLSI layout spacingproblems with multiple variable constraints.
Volume 20, Number 9, September 2001
, Yean-Yow Hwang
: Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping.
Arlindo L. Oliveira
: Techniques for the creation of digital watermarks in sequentialcircuit designs.
Volume 20, Number 10, October 2001
Volume 20, Number 11, November 2001
, Alex Orailoglu
: Performance and power effectiveness in embedded processors customizable partitioned caches.
Volume 20, Number 12, December 2001
: Effect of the switching order on power dissipation inswitched-capacitor circuits.
: A comparison of strong and weak distributed transverse couplingbetween VLSI interconnects.