Volume 21, Number 1, January 2002
Volume 21, Number 2, February 2002
Yehea I. Ismail
, Eby G. Friedman
: DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect.
Volume 21, Number 3, March 2002
Volume 21, Number 4, April 2002
: Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead.
Volume 21, Number 5, May 2002
, Wen-Ben Jone
: A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations.
, Sudhakar M. Reddy
: Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults.
Volume 21, Number 6, June 2002
, Ajoy Opal
: An efficient transient analysis algorithm for mildly nonlinearcircuits.
, Sudhakar M. Reddy
: Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences.
, T. Sakurai
: Power distribution analysis of VLSI interconnects using model orderreduction.
Volume 21, Number 7, July 2002
: A probably approximately correct framework to estimate performancedegradation in embedded systems.
: Transient simulation of high-speed interconnects based on thesemidiscretization of Telegrapher's equations.
Volume 21, Number 8, August 2002
Volume 21, Number 9, September 2002
: On the use of random limited-scan to improve at-speed randompattern testing of scan circuits.
, Ramesh Karri
: Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection.
Volume 21, Number 10, October 2002
: Comments on "Filling algorithms and analyses for layout density control".
Volume 21, Number 11, November 2002
, Charlie Chung-Ping Chen
: Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method.
: Publicly detectable watermarking for intellectual property authentication in VLSI design.
Volume 21, Number 12, December 2002
: Formulating SoC test scheduling as a network transportation problem.
, Hyeong-Ju Kang
: Digital filter synthesis based on an algorithm to generate all minimal signed digit representations.