IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 27

Volume 27, Number 1, January 2008

• Enrico Macii:
  Editorial. 1-2
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• Andrew B. Kahng, Kambiz Samadi:
  CMP Fill Synthesis: A Survey of Recent Studies. 3-19
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• Josep Carmona, Jordi Cortadella:
  Encoding Large Asynchronous Controllers With ILP Techniques. 20-33
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• Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi:
  Two-Dimensional Schemes for Clocking/Timing of QCA Circuits. 34-44
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• Shrirang K. Karandikar, Sachin S. Sapatnekar:
  Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. 45-58
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• Ting Mei, Jaijeet S. Roychowdhury:
  A Time-Domain Oscillator Envelope Tracking Algorithm Employing Dual Phase Conditions. 59-69
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• Chris C. N. Chu, Yiu-Chung Wong:
  FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. 70-83
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• Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger:
  Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards. 84-95
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• Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha:
  System-Level Dynamic Thermal Management for High-Performance Microprocessors. 96-108
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• Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen:
  A Reactive and Cycle-True IP Emulator for MPSoC Exploration. 109-122
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• Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras:
  Experimental Characterization of CMOS Interconnect Open Defects. 123-136
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• Irith Pomeranz, Sudhakar M. Reddy:
  Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. 137-146
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• Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Neelanjan Mukherjee, Mark Kassab:
  X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. 147-159
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• Jaskirat Singh, Sachin S. Sapatnekar:
  A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations. 160-173
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• Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy:
  Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. 174-183
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• Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
  Fixing Design Errors With Counterexamples and Resynthesis. 184-188
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• Sushanta K. Mandal, Shamik Sural, Amit Patra:
  ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs. 188-192
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• Irith Pomeranz, Sudhakar M. Reddy:
  Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. 193-197
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• Weixin Wu, Michael S. Hsiao:
  Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking. 197-201
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Volume 27, Number 2, February 2008

• Javid Jaffari, Mohab Anis:
  Variability-Aware Bulk-MOS Device Design. 205-216
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• R. Mahesh, A. Prasad Vinod:
  A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters. 217-229
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• Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma:
  Defocus-Aware Leakage Estimation and Control. 230-240
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• Ja Chun Ku, Yehea I. Ismail:
  Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. 241-248
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• Ning Dong, Jaijeet S. Roychowdhury:
  General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations. 249-264
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• Alexander Heldring, Juan M. Rius, José Maria Tamayo, Josep Parrón:
  Compressed Block-Decomposition Algorithm for Fast Capacitance Extraction. 265-271
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• Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw:
  A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. 272-285
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• Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin:
  A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. 286-294
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• Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar:
  A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation. 295-308
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• Shantanu Dutt, Vinay Verma, Vishal Suthar:
  Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing. 309-326
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• Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker:
  On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. 327-338
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• Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
  Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing. 339-351
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• Zhanglei Wang, Krishnendu Chakrabarty:
  Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns. 352-365
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• Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke:
  Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog. 366-379
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• Ilya Wagner, Valeria Bertacco, Todd M. Austin:
  Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. 380-393
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• Hiren D. Patel, Sandeep K. Shukla:
  On Cosimulating Multiple Abstraction-Level System-Level Models. 394-398
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• Irith Pomeranz, Sudhakar M. Reddy:
  Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. 398-403
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• Aleksandra Sesic, Stanisa Dautovic, Veljko Malbasa:
  Dynamic Power Management of a System With a Two-Priority Request Queue Using Probabilistic-Model Checking. 403-407
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Volume 27, Number 3, March 2008

• Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh:
  Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration. 409-422
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• Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
  Scalable Synthesis and Clustering Techniques Using Decision Diagrams. 423-435
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• Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, C. Negrevergne:
  Quantum Circuit Simplification and Level Compaction. 436-444
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• Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
  Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. 445-455
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• Kin Cheong Sou, Alexandre Megretski, Luca Daniel:
  A Quasi-Convex Optimization Approach to Parameterized Model Order Reduction. 456-469
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• Ngai Wong:
  Efficient Positive-Real Balanced Truncation of Symmetric Systems Via Cross-Riccati Equations. 470-480
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• Sarvesh H. Kulkarni, D. M. Sylvester, David T. Blaauw:
  Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias. 481-494
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• Baolin Yang, Yu Zhu, Ali Bouaricha, Joel R. Phillips:
  Applications of the Multi-Interval Chebyshev Collocation Method in RF Circuit Simulation. 495-507
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• Peter Hallschmid, Resve Saleh:
  Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. 508-515
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• Seda Ogrenci Memik, Rajarshi Mukherjee, Min Ni, Jieyi Long:
  Optimizing Thermal Sensor Allocation for Microprocessors. 516-527
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• Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk:
  CHIPS: Custom Hardware Instruction Processor Synthesis. 528-541
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• Hristo Nikolov, Todor Stefanov, Ed F. Deprettere:
  Systematic and Automated Multiprocessor System Design, Programming, and Implementation. 542-555
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• Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar:
  An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. 556-569
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• Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda:
  An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores. 570-574
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• Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub:
  A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform. 574-578
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• Chaeho Chung, Soobum Lee, Byung Man Kwak, Gawon Kim, Joungho Kim:
  A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm. 578-583
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• Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
  On Complete Functional Broadside Tests for Transition Faults. 583-587
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Volume 27, Number 4, April 2008

• David Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer:
  Statistical Timing Analysis: From Basic Principles to State of the Art. 589-607
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• Patrick H. Madden, David Z. Pan:
  Guest Editorial. 608-609
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• Vishal Khandelwal, Ankur Srivastava:
  Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. 610-620
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• Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
  Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. 621-632
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• Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
  Fast Dummy-Fill Density Analysis With Coupling Constraints. 633-642
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• Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang:
  Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. 643-653
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• Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang:
  Effective Wire Models for X-Architecture Placement. 654-658
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• Cheoljoo Jeong, Steven M. Nowick:
  Technology Mapping and Cell Merger for Asynchronous Threshold Networks. 659-672
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• Seok-Won Seong, Prabhat Mishra:
  Bitmask-Based Code Compression for Embedded Systems. 673-685
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• Ryan Fung, Vaughn Betz, William Chow:
  Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations. 686-697
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• Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew:
  GfXpress: A Technique for Synthesis and Optimization of GF(2^m) Polynomials. 698-711
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• Ying Wei, Alex Doboli:
  Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation. 712-725
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• Zhen Cao, Tong T. Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong:
  Fashion: A Fast and Accurate Solution to Global Routing Problem. 726-737
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• Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen:
  Power Grid Analysis and Optimization Using Algebraic Multigrid. 738-751
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• Dmitri Maslov, Sean M. Falconer, Michele Mosca:
  Quantum Circuit Placement. 752-763
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• Neil Kettle, Andy King:
  An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs. 764-777
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Volume 27, Number 5, May 2008

• Paolo Maffezzoni:
  Unified Computation of Parameter Sensitivity and Signal-Injection Sensitivity in Nonlinear Oscillators. 781-790
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• Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi:
  Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach. 791-802
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• Natasa Miskov-Zivanov, Diana Marculescu:
  Modeling and Optimization for Soft-Error Reliability of Sequential Circuits. 803-816
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• S. Srivastava, J. Roychowdhury:
  Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations. 817-830
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• Xin Li, Yaping Zhan, Lawrence T. Pileggi:
  Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits. 831-843
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• Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han:
  Full-Chip Routing Considering Double-Via Insertion. 844-857
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• Song Chen, Takeshi Yoshimura:
  Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs. 858-871
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• Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan:
  Track Routing and Optimization for Yield. 872-882
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• Bo Hu, C.-J. Richard Shi:
  Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis. 883-892
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• Diana Marculescu, Siddharth Garg:
  Process-Driven Variability Analysis of Single and Multiple Voltage-Frequency Island Latency-Constrained Systems. 893-905
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• Claudio Pinello, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
  Fault-Tolerant Distributed Deployment of Embedded Control Software. 906-919
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• Erkan Acar, Sule Ozev:
  Defect-Oriented Testing of RF Circuits. 920-931
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• Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
  Improving the Resolution of Single-Delay-Fault Diagnosis. 932-945
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• Irith Pomeranz, Sudhakar M. Reddy:
  On the Saturation of n-Detection Test Generation by Different Definitions With Increased n. 946-957
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• Jeong-Ho Han, In-Cheol Park:
  FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient. 958-962
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• Xiaojun Ma, Fabrizio Lombardi:
  Synthesis of Tile Sets for DNA Self-Assembly. 963-967
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• Bhaskar Pal, Ansuman Banerjee, Arnab Sinha, Pallab Dasgupta:
  Accelerating Assertion Coverage With Adaptive Testbenches. 967-972
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• Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng:
  Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling. 973-977
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• Gülin Tulunay, Sina Balkir:
  A Synthesis Tool for CMOS RF Low-Noise Amplifiers. 977-982
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Volume 27, Number 6, June 2008

• Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang:
  Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis. 985-998
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• Dong Xiang, Yang Zhao, K. Chakrabarty, Hideo Fujiwara:
  A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. 999-1012
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• Levent Aksoy, Eduardo da Costa, Paulo F. Flores, José Monteiro:
  Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. 1013-1026
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• Javid Jaffari, Mohab Anis:
  Statistical Thermal Profile Considering Process Variations: Analysis and Applications. 1027-1040
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• Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi:
  Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. 1041-1054
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• Zhe-Wei Jiang, Yao-Wen Chang:
  An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing. 1055-1065
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• Jarrod A. Roy, Igor L. Markov:
  High-Performance Routing at the Nanometer Scale. 1066-1077
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• Pramod Chandraiah, Rainer Dömer:
  Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding. 1078-1090
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• Tarvo Raudvere, Ingo Sander, Axel Jantsch:
  Application and Verification of Local Nonsemantic-Preserving Transformations in System Design. 1091-1103
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• Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li:
  Diagnosis of Multiple Scan Chain Timing Faults. 1104-1116
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• S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosinger, Bashir M. Al-Hashimi, Peter Harrod:
  Bridging Fault Test Method With Adaptive Power Management Awareness. 1117-1127
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• Afshin Abdollahi, Massoud Pedram:
  Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions. 1128-1137
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• Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler:
  Automatic Fault Localization for Property Checking. 1138-1149
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• Brajesh Kumar Kaushik, Sankar Sarkar:
  Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects. 1150-1154
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• Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie:
  Register File Power Reduction Using Bypass Sensitive Compiler. 1155-1159
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• Lin Yuan, Gang Qu, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli:
  An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting. 1159-1164
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Volume 27, Number 7, July 2008

• Vijay D'Silva, Daniel Kroening, Georg Weissenbacher:
  A Survey of Automated Techniques for Formal Software Verification. 1165-1178
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• R. Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández:
  An Integrated Layout-Synthesis Approach for Analog ICs. 1179-1189
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• Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa:
  Logic Minimization and Testability of 2-SPP Networks. 1190-1202
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• Lei Cheng, Deming Chen, Martin D. F. Wong:
  DDBDD: Delay-Driven BDD Synthesis for FPGAs. 1203-1213
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• Taehoon Kim, Yungseon Eo:
  Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled RLC Interconnect Lines. 1214-1227
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• Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
  NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. 1228-1240
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• Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu:
  Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion. 1241-1252
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• Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He:
  Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations. 1253-1263
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• Soner Yaldiz, Alper Demir, Serdar Tasiran:
  Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study. 1264-1277
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• Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
  Low-Power Test Data Application in EDT Environment Through Decompressor Freeze. 1278-1290
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• Sari Onaissi, Farid N. Najm:
  A Linear-Time Approach for Static Timing Analysis Covering All Process Corners. 1291-1304
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• Daniel Große, Ulrich Kühne, Rolf Drechsler:
  Analyzing Functional Coverage in Bounded Model Checking. 1305-1314
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• Xiaoxi Xu, Cheng-Chew Lim:
  Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip. 1315-1328
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• Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille:
  On Acceleration of SAT-Based ATPG for Industrial Designs. 1329-1333
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• Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
  Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability. 1333-1338
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• Jing-Ling Yang, Qiang Xu:
  State-Sensitive X-Filling Scheme for Scan Capture Power Reduction. 1338-1343
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• Hao Zheng, Jared Ahrens, Tian Xia:
  A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification. 1343-1347
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Volume 27, Number 8, August 2008

• Jason Cong, Min Xie:
  A Robust Mixed-Size Legalization and Detailed Placement Algorithm. 1349-1362
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• Chih-Hung Liu, Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Yao-Wen Chang, Sy-Yen Kuo, Shih-Yi Yuan, Yu-Wei Chen:
  An Efficient Graph-Based Algorithm for ESD Current Path Analysis. 1363-1375
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• Maharaj Mukherjee, Kanad Chakraborty:
  A Randomized Greedy Method for Rectangular-Pattern Fill Problems. 1376-1384
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• Uday Padmanabhan, Janet Meiling Wang, Jiang Hu:
  Robust Clock Tree Routing in the Presence of Process Variations. 1385-1397
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• Peter Spindler, Ulf Schlichtmann, Frank M. Johannes:
  Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model. 1398-1411
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• Giovanni Agosta, Francesco Bruschi, Donatella Sciuto:
  Static Analysis of Transaction-Level Communication Models. 1412-1424
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• Karam S. Chatha, Krishnan Srinivasan, Goran Konjevod:
  Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures. 1425-1438
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• Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt:
  Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. 1439-1452
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• Ozgur Sinanoglu, Tsvetomir Petrov:
  Isolation Techniques for Soft Cores. 1453-1466
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• Changjiu Xian, Yung-Hsiang Lu, Zhiyuan Li:
  Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time. 1467-1478
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• Changyun Zhu, Zhenyu Gu, Li Shang, Robert P. Dick, Russ Joseph:
  Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. 1479-1492
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• Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan Mandal, Amit Patra:
  A Fast Exploration Procedure for Analog High-Level Specification Translation. 1493-1497
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• King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang:
  Dual-V_dd Buffer Insertion for Power Reduction. 1498-1502
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• Shuai Wang, Jie Hu, Sotirios G. Ziavras:
  Self-Adaptive Data Caches for Soft-Error Reliability. 1503-1507
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• Wenjian Yu, Xiren Wang, Zuochang Ye, Zeyi Wang:
  Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method. 1508-1513
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• Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar:
  Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking. 1513-1517
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Volume 27, Number 9, September 2008

• Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
  Sensitivity Analysis for Oscillators. 1521-1534
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• Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi:
  A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. 1535-1544
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• Y.-J. J. Yang, C.-W. Kuo:
  Generating Scalable and Modular Macromodels for Microchannels Using the Galerkin-Based Technique. 1545-1554
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• Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
  Input Vector Reordering for Leakage Power Reduction in FPGAs. 1555-1564
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• Aijiao Cui, Chip-Hong Chang, Sofiène Tahar:
  IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. 1565-1570
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• Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng:
  Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process. 1571-1582
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• Hiran Tennakoon, Carl Sechen:
  Nonconvex Gate Delay Modeling and Delay Optimization. 1583-1594
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• Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram:
  Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method. 1595-1606
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• Ulrich Brenner, Markus Struzyna, Jens Vygen:
  BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms. 1607-1620
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• Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu:
  MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. 1621-1634
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• Andrew B. Kahng, Chul-Hong Park, Xu Xu:
  Fast Dual-Graph-Based Hotspot Filtering. 1635-1642
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• T.-H. Lee, T.-C. Wang:
  Congestion-Constrained Layer Assignment for Via Minimization in Global Routing. 1643-1656
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• Munkang Choi, Linda S. Milor:
  Diagnosis of Optical Lithography Faults With Product Test Sets. 1657-1669
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• Fu-Ching Yang, Wen-Kai Huang, J.-K. Zhong, Ing-Jer Huang:
  Automatic Verification of External Interrupt Behaviors for Microprocessor Design. 1670-1683
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• J.-C. Guo, Y.-M. Lin:
  A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs. 1684-1688
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• Jayawant Kakade, Dimitrios Kagaris, Dhiraj K. Pradhan:
  Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs. 1689-1692
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• H.-C. Liang, P.-H. Huang, Y.-F. Tang:
  Testing Transition Delay Faults in Modified Booth Multipliers. 1693-1697
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