Volume 29, Number 1, January 2010
Sachin S. Sapatnekar: Editorial. 1- Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy: Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations. 2-13
- Sandra Lefteriu, Athanasios C. Antoulas: A New Approach to Modeling Multiport Systems From Frequency-Domain Data. 14-27
- Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang: Predictive Formulae for OPC With Applications to Lithography-Friendly Routing. 40-50
- Siew-Hong Teh, Chun-Huat Heng, Arthur Tay: Performance-Based Optical Proximity Correction Methodology. 51-64
- Nick Soveiko, Michel S. Nakhla, Ramachandra Achar: Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures. 65-77
- Chen-Ling Chou, Radu Marculescu: Run-Time Task Allocation Considering User Behavior in Embedded Multiprocessor Networks-on-Chip. 78-91
- Imad A. Ferzli, Eli Chiprout, Farid N. Najm: Verification and Codesign of the Package and Die Power Delivery System Using Wavelets. 92-102
- Qiaoyan Yu, Paul Ampadu: A Flexible Parallel Simulator for Networks-on-Chip With Error Control. 103-116
- Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: On Compaction Utilizing Inter and Intra-Correlation of Unknown States. 117-126
- Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Foster: Increasing the Efficiency of Simulation-Based Functional Verification Through Unsupervised Support Vector Analysis. 138-148
- G. Chen: Formalization of a Parameterized Parallel Adder Within the Coq Theorem Prover. 149-153
- Benjamin Carrión Schäfer, Kazutoshi Wakabayashi: Design Space Exploration Acceleration Through Operation Clustering. 153-157
- Luís Guerra e Silva, Joel R. Phillips, Luis Miguel Silveira: Effective Corner-Based Techniques for Variation-Aware IC Timing Verification. 157-162
Volume 29, Number 2, February 2010
- Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang: Enhanced Double Via Insertion Using Wire Bending. 171-184
- Kun Yuan, Jae-Seok Yang, David Z. Pan: Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization. 185-196
- Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly: Layout Generator for Transistor-Level High-Density Regular Circuits. 197-210
- Qunzeng Liu, Sachin S. Sapatnekar: Capturing Post-Silicon Variations Using a Representative Critical Path. 211-222
- Yifang Liu, Jiang Hu: A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. 223-234
- Quang Dinh, Deming Chen, Martin D. F. Wong: A Routing Approach to Reduce Glitches in Low Power FPGAs. 235-240
- Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang: A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations. 240-245
- Rupesh S. Shelar: Routing With Constraints for Post-Grid Clock Distribution in Microprocessors. 245-249
- Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue: Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. 250-260
- Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester: Victim Alignment in Crosstalk-Aware Timing Analysis. 261-274
- Raveendranatha P. Mahesh, A. Prasad Vinod: New Reconfigurable Architectures for Implementing FIR Filters With Low Complexity. 275-288
- Wen-Wen Hsieh, S.-L. Chen, I-Sheng Lin, TingTing Hwang: A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test. 289-298
- Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone: Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. 299-312
- J.-E. Chen, P.-W. Luo, C.-L. Wey: Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits. 313-318
- Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao: Optimal Double Via Insertion With On-Track Preference. 318-323
Volume 29, Number 3, March 2010
- Hao Zheng: Compositional Reachability Analysis for Efficient Modular Verification of Asynchronous Designs. 329-340
- Ajay K. Verma, Philip Brisk, Paolo Ienne: Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. 341-354
- Hyein Lee, Seungwhun Paik, Youngsoo Shin: Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches. 355-366
- Jackey Z. Yan, Chris Chu: DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm. 367-381
- Gianpiero Cabodi, Luz Amanda Garcia, Marco Murciano, Sergio Nocco, Stefano Quer: Partitioning Interpolant-Based Verification for Effective Unbounded Model Checking. 382-395
- Mingsong Chen, Prabhat Mishra: Functional Test Generation Using Efficient Property Clustering and Learning Techniques. 396-404
- Adam B. Kinsman, Nicola Nicolici: Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory. 405-413
- Matin Hashemi, Soheil Ghiasi: Versatile Task Assignment for Heterogeneous Soft Dual-Processor Platforms. 414-425
- Maurizio Palesi, Shashi Kumar, Vincenzo Catania: Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip. 426-440
- Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. 441-453
- Irith Pomeranz, Sudhakar M. Reddy: TOV: Sequential Test Generation by Ordering of Test Vectors. 454-465
- Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. 466-478
- Chandan Karfa, Dipankar Sarkar, Chitta Mandal: Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. 479-492
- Enric Musoll: Hardware-Based Load Balancing for Massive Multicore Architectures Implementing Power Gating. 493-497
- Seung Hoon Choi, Kunhyuk Kang, Florentin Dartu, Kaushik Roy: Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching. 497-502
Volume 29, Number 4, April 2010
- Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry T. Pileggi, Andrzej J. Strojwas, Jason Hibbeler: Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings. 509-527
- Angelo Brambilla, Giambattista Gruosso, Giancarlo Storti Gajani: FSSA: Fast Steady-State Algorithm for the Analysis of Mixed Analog/Digital Circuits. 528-537
- Akash Kumar, Bart Mesman, Henk Corporaal, Yajun Ha: Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems. 538-551
- Tao Xu, Krishnendu Chakrabarty, Vamsee K. Pamula: Defect-Tolerant Design and Optimization of a Digital Microfluidic Biochip for Protein Crystallization. 552-565
- Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta: Translation Validation of High-Level Synthesis. 566-579
- Jui-Hsiang Liu, Ming-Feng Tsai, Lumdo Chen, Charlie Chung-Ping Chen: Accurate and Analytical Statistical Spatial Correlation Modeling Based on Singular Value Decomposition for VLSI DFM Applications. 580-589
- Sangho Shin, Kyungmin Kim, Sung-Mo Kang: Compact Models for Memristors Based on Charge-Flux Constitutive Relationships. 590-598
- Xin Li, Colin C. McAndrew, Weimin Wu, Samir Chaudhry, James Victory, Gennady Gildenblat: Statistical Modeling With the PSP MOSFET Model. 599-606
- Katherine Shu-Min Li: Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction Under Output Constraint. 618-626
- Rajesh Amratlal Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Mahesh B. Patil: A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance. 627-631
- Stephen Cauley, Venkataramanan Balakrishnan, Cheng-Kok Koh: A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks. 636-641
- Taemin Kim, Xun Liu: A Functional Unit and Register Binding Algorithm for Interconnect Reduction. 641-646
- Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo: Accurately Handle Don't-Care Conditions in High-Level Designs and Application for Reducing Initialized Registers. 646-651
Volume 29, Number 5, May 2010
- Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin: HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. 657-670
- Yang-Shan Tong, Sao Jie Chen: An Automatic Optical Simulation-Based Lithography Hotspot Fix Flow for Post-Route Optimization. 671-684
- Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang: Multilayer Global Routing With Via and Wire Capacity Considerations. 685-696
- Kuan-Hsien Ho, Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang: ECO Timing Optimization Using Spare Cells and Technology Remapping. 697-710
- Jia-Wei Fang, Yao-Wen Chang: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews. 711-721
- Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Mechanical Stress Aware Optimization for Leakage Power Reduction. 722-736
- Bijan Alizadeh, Mohammad Mirzaei, Masahiro Fujita: Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits. 737-748
- Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chandu Visweswariah: Statistical Path Selection for At-Speed Test. 749-759
- Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor: Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits. 760-773
- Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar: A Cost Effective Approach for Online Error Detection Using Invariant Relationships. 788-801
- Yue Qian, Zhonghai Lu, Wenhua Dou: Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks. 802-815
- Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward: Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. 816-829
- Svetozar S. Broussev, Nikolay T. Tchamov: Time-Varying Root-Locus of Large-Signal LC Oscillators. 830-834
- Chao-Wen Tzeng, Shi-Yu Huang: Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression. 834-839
- Abraham Suissa, Olivier Romain, Julien Denoulet, Khalil Hachicha, Patrick Garda: Empirical Method Based on Neural Networks for Analog Power Modeling. 839-844
- Chip-Hong Chang, Mathias Faust: On "A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters". 844-848
- Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee: Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. 849
Volume 29, Number 6, June 2010
- Radu Marculescu, Axel Jantsch: Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2009. 853-854
- Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad: Virtual Point-to-Point Connections for NoCs. 855-868
- Nicola Concer, Luciano Bononi, Michael Soulie, Riccardo Locatelli, Luca P. Carloni: The Connection-Then-Credit Flow Control Protocol for Heterogeneous Multicore Systems-on-Chip. 869-882
- Adán Kohler, Gert Schley, Martin Radetzki: Fault Tolerant Network on Chip Switching With Graceful Performance Degradation. 883-896
- Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas: A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms. 897-910
- Fabrizio Ferrandi, Pier Luca Lanzi, Christian Pilato, Donatella Sciuto, Antonino Tumeo: Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems. 911-924
- Jorge Fernandez Villena, Luis Miguel Silveira: SPARE - A Scalable Algorithm for Passive, Structure Preserving, Parameter-Aware Model Order Reduction. 925-938
- Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao: Layout Decomposition Approaches for Double Patterning Lithography. 939-952
- Chin-Hsien Wu, Hsin-Hung Lin, Tei-Wei Kuo: An Adaptive Flash Translation Layer for High-Performance Storage Systems. 953-965
- Zhen Chen, Dong Xiang: A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost. 966-976
- Xiaochun Yu, Ronald D. Blanton: Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics. 977-987
- Xiaoxi Xu, Cheng-Chew Lim: Modeling Interrupts for Software-Based System-on-Chip Verification. 993-997
Volume 29, Number 7, July 2010
- Krishnendu Chakrabarty, Richard B. Fair, Jun Zeng: Design Tools for Digital Microfluidic Biochips: Toward Functional Diversification and More Than Moore. 1001-1017
- Jongeun Lee, Aviral Shrivastava: A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files. 1018-1027
- Soumyajit Dey, Dipankar Sarkar, Anupam Basu: A Tag Machine Based Performance Evaluation Method for Job-Shop Schedules. 1028-1041
- Vincent Acary, Olivier Bonnefon, Bernard Brogliato: Time-Stepping Numerical Simulation of Switched Circuits Within the Nonsmooth Dynamical Systems Approach. 1042-1055
- Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan: Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. 1056-1069
- Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao: Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. 1070-1082
- Giovanni Beltrame, Luca Fossati, Donatella Sciuto: Decision-Theoretic Design Space Exploration of Multiprocessor Platforms. 1083-1095
- Philip Brisk, Ajay K. Verma, Paolo Ienne: An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. 1096-1109
- Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak: On Reducing Scan Shift Activity at RTL. 1110-1120
- Dani Tannir, Roni Khazaka: Computation of Intermodulation Distortion in RF Circuits Using Single-Tone Moments Analysis. 1121-1125
- Daniel Tille, Stephan Eggersglüß, Rolf Drechsler: Incremental Solving Techniques for SAT-based ATPG. 1125-1130
- Myung-Hoon Yang, Hyungjun Cho, Wooheon Kang, Sungho Kang: EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate. 1130-1135
- Irith Pomeranz, Sudhakar M. Reddy: On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits. 1135-1140
- Likun Xia, Ian M. Bell, Antony J. Wilkinson: Automated Model Generation Algorithm for High-Level Fault Modeling. 1140-1145
Volume 29, Number 8, August 2010
- Bradley N. Bond, Zohaib Mahmood, Yan Li, Ranko Sredojevic, Alexandre Megretski, Vladimir Stojanovic, Yehuda Avniel, Luca Daniel: Compact Modeling of Nonlinear Analog Circuits Using System Identification via Semidefinite Programming and Incremental Stability Certification. 1149-1162
- Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: FPGA Architecture Optimization Using Geometric Programming. 1163-1176
- Yu Pang, Katarzyna Radecka, Zeljko Zilic: Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials. 1177-1190
- ShengYu Shen, Ying Qin, KeFei Wang, LiQuan Xiao, Jianmin Zhang, Sikun Li: Synthesizing Complementary Circuits Automatically. 1191-1202
- Zheng Zhang, Ngai Wong: An Efficient Projector-Based Passivity Test for Descriptor Systems. 1203-1214
- Onder Suvak, Alper Demir: Quadratic Approximations for the Isochrons of Oscillators: A General Theory, Advanced Numerical Methods, and Accurate Phase Computations. 1215-1228
- Mohit Gupta, Kwangok Jeong, Andrew B. Kahng: Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography. 1229-1242
- Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu: Built-In Self-Repair Schemes for Flash Memories. 1243-1256
- De-Shiuan Chiou, Yu-Ting Chen, Da-Cheng Juan, Shih-Chieh Chang: Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation. 1285-1289
- Amir Beygi, Anestis Dounavis: Sensitivity Analysis of Lossy Multiconductor Transmission Lines Based on the Passive Method of Characteristics Macromodel. 1290-1294
- Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Improved Launch for Higher TDF Coverage With Fewer Test Patterns. 1294-1299
Volume 29, Number 9, September 2010
- Chen-Ling Chou, Radu Marculescu: Designing Heterogeneous Embedded Network-on-Chip Platforms With Users in Mind. 1301-1314
- Cliff Chiung-Yu Lin, Yao-Wen Chang: ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips. 1315-1327
- Alp Arslan Bayrakci, Alper Demir, Serdar Tasiran: Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation. 1328-1341
- Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu: Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. 1342-1353
- Timo Reis, Tatjana Stykel: PABTEC: Passivity-Preserving Balanced Truncation for Electrical Circuits. 1354-1367
- Sina Meraji, Wei Zhang, Carl Tropper: On the Scalability and Dynamic Load-Balancing of Optimistic Gate Level Simulation. 1368-1380
- Kyungsu Kang, Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung: Temperature-Aware Integrated DVFS and Power Gating for Executing Tasks With Runtime Distribution. 1381-1394
- Hwisung Jung, Massoud Pedram: Supervised Learning Based Power Management for Multicore Processors. 1395-1408
- S. Saqib Khursheed, Bashir M. Al-Hashimi, Krishnendu Chakrabarty, Peter Harrod: Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs. 1409-1421
- Bijan Alizadeh, Masahiro Fujita: Modular Datapath Optimization and Verification Based on Modular-HED. 1422-1435
- Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic: Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. 1436-1448
- Irith Pomeranz, Sudhakar M. Reddy: Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage. 1449-1453
Volume 29, Number 10, October 2010
- Eric S. Chung, James C. Hoe: High-Level Design and Validation of the BlueSPARC Multithreaded Processor. 1459-1470
- Xavier Briand, Bertrand Jeannet: Combining Control and Data Abstraction in the Verification of Hybrid Systems. 1481-1494
- Peter Böhm: Incremental and Verified Modeling of the PCI Express Protocol. 1495-1508
- Mingjie Lin, John Wawrzynek, Abbas El Gamal: Exploring FPGA Routing Architecture Stochastically. 1509-1522
- João M. S. Silva, Joel R. Phillips, Luis Miguel Silveira: Efficient Simulation of Power Grids. 1523-1532
- Ashutosh Chakraborty, Sean X. Shi, David Z. Pan: Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement. 1533-1545
- Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng: Multicore Parallelization of Min-Cost Flow for CAD Applications. 1546-1557
- Mohammad Arjomand, Hamid Sarbazi-Azad: Power-Performance Analysis of Networks-on-Chip With Arbitrary Buffer Allocation Schemes. 1558-1571
- Shervin Sharifi, Tajana Simunic Rosing: Accurate Direct and Indirect On-Chip Temperature Sensing for Efficient Dynamic Thermal Management. 1586-1599
- Hoeseok Yang, Sungchan Kim, Soonhoi Ha: An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC. 1600-1613
- Natasa Miskov-Zivanov, Diana Marculescu: Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach. 1614-1627
- Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li: DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs. 1628-1639
- Vasileios Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros: Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores. 1640-1644
- Chih-Yen Lo, Yu-Tsao Hsing, Li-Ming Denq, Cheng-Wen Wu: SOC Test Architecture and Method for 3-D ICs. 1645-1649
- Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer: Interconnect Bundle Sizing Under Discrete Design Rules. 1650-1654
- Feng Liu, Xiaoyu Song, Qingping Tan, Gang Chen: Formal Analysis of End-Around-Carry Adder in Floating-Point Unit. 1655-1659
Volume 29, Number 11, November 2010
- Xin Li: Finding Deterministic Solution From Underdetermined Equation: Large-Scale Performance Variability Modeling of Analog/RF Circuits. 1661-1668
- Mauro Ballicchia, Simone Orcioni: Design and Modeling of Optimum Quality Spiral Inductors With Regularization and Debye Approximation. 1669-1681
- Tsung-Wei Huang, Chun-Hsien Lin, Tsung-Yi Ho: A Contamination Aware Droplet Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. 1682-1695
- Sudip Roy, Bhargab B. Bhattacharya, Krishnendu Chakrabarty: Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips. 1696-1708
- Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng: Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. 1709-1722
- Tomasz S. Czajkowski, Stephen Dean Brown: Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits. 1723-1735
- Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet: High-Level Synthesis for Designing Multimode Architectures. 1736-1749
- Amith Singhee, Rob A. Rutenbar: Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis. 1763-1776
- Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran: Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems. 1777-1789
- Yibin Chen, Sean Safarpour, João Marques-Silva, Andreas G. Veneris: Automated Design Debugging With Maximum Satisfiability. 1804-1817
- Gregory Lucas, Chen Dong, Deming Chen: Variation-Aware Placement With Multi-Cycle Statistical Timing Analysis for FPGAs. 1818-1822
- Jintae Kim, Lieven Vandenberghe, Chih-Kong Ken Yang: Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming. 1823-1827
- Yung-Chih Chen, Chun-Yao Wang: Fast Node Merging With Don't Cares Using Logic Implications. 1827-1832
- Po-Lin Chen, Yu-Chieh Huang, Tsin-Yuan Chang: Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500. 1837-1842
- Jin-Fu Li, Yu-Jen Huang, Yong-Jyun Hu: Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells. 1843-1847
Volume 29, Number 12, December 2010
- Paolo Maffezzoni: Computing the Synchronization Regions of Injection-Locked Strongly Nonlinear Oscillators for Frequency Division Applications. 1849-1857
- Mingjie Lin, John Wawrzynek: Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling. 1858-1869
- Pongstorn Maidee, Kia Bazargan: Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits. 1870-1883
- Elie Maricau, Georges G. E. Gielen: Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis. 1884-1893
- Javid Jaffari, Mohab Anis: Advanced Variance Reduction and Sampling Techniques for Efficient Statistical Timing Analysis. 1894-1907
- Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun: Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs. 1908-1920
- Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang: Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers. 1921-1930
- Yen-Jung Chang, Yu-Ting Lee, Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang: NTHU-Route 2.0: A Robust Global Router for Modern Designs. 1931-1944
- Anand Rajaram, David Z. Pan: MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis. 1945-1958
- Xiangyu Dong, Jishen Zhao, Yuan Xie: Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs. 1959-1972
- Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohammad Hossien Yaghmaee: Buffer Optimization in Network-on-Chip Through Flow Regulation. 1973-1986
- Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli: SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips. 1987-2000
- Ümit Y. Ogras, Paul Bogdan, Radu Marculescu: An Analytical Approach for Network-on-Chip Performance Analysis. 2001-2013
- Woosik Jeong, Joohwan Lee, Taewoo Han, Kaangchil Lee, Sungho Kang: An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer. 2014-2026
- Sergio Nocco, Stefano Quer: A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem. 2027-2040
- Yongho Jang, Jungsoo Kim, Chong-Min Kyung: Topology Synthesis for Low Power Cascaded Crossbar Switches. 2041-2045
- Fu-Wei Chen, Yi-Yu Liu: Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style. 2046-2050
- Sunghoon Chun, Alex Orailoglu: DiSC: A New Diagnosis Method for Multiple Scan Chain Failures. 2051-2055
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last updated on 2013-06-18T211851 by the dblp team